INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT
An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.
1 - 17 . (canceled)
18 . A method of making a semiconductor device comprising:
forming a first N channel transistor that is used in a logic circuit;
forming a first P channel transistor that is used in the logic circuit;
forming a second N channel transistor that is used in a SRAM array;
forming a second P channel transistor that is used in the SRAM array;
depositing a first dielectric layer over the semiconductor device that has a first stress;
removing the first dielectric layer over the first and second P channel transistors;
depositing a second dielectric layer over the semiconductor device that has a second stress that is more compressive than the first stress; and
removing the second layer over the first and second N channel transistors and the second P channel transistor;
depositing a third dielectric layer over the semiconductor device that has a third stress that is between the first stress and the second stress;
removing the third dielectric layer over the first and second N channel transistors and the first P channel transistor.
19 . A method of making a semiconductor device comprising:
forming a first N channel transistor that is used in a logic circuit;
forming a first P channel transistor that is used in the logic circuit;
forming a second N channel transistor that is used in a SRAM array;
forming a second P channel transistor that is used in the SRAM array;
depositing a first dielectric layer over the semiconductor device that has a first stress;
removing the first dielectric layer over the first and second P channel transistors;
depositing a second dielectric layer over the semiconductor device that has a second stress that is more compressive than the first stress; and
removing the second dielectric layer over the first and second N channel transistors whereby a first portion of the second dielectric layer is left on the first P channel transistor and a second portion of the second dielectric layer is left over the second P channel transistor; and
implanting into the second portion of the second dielectric layer to cause the second portion of the second dielectric layer to become less compressive.
20 . A method of making a semiconductor device, comprising:
forming a first portion comprising a first transistor of the first type and a first transistor of a second type for use in a circuit of a first type;
forming a second portion comprising a second transistor of the first type and a second transistor of the second type for use in a circuit of a second type;
forming a first ILD over the first transistor of the first type having a first stress of a first type; and
forming a second ILD over the second transistor of the first type having a second stress that is at least less than the first stress of the first type.