Read conditions for a non-volatile memory (NVM)
View Patent ↗A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing an erase operation of the plurality of non-volatile memory cells; determining an erase level of a least erased memory cell of the plurality of memory cells; determining an operating window between the program level and the erase level; and setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value. The memory includes registers for storing the program level and the erase level.
1. A method for determining a read reference level for a plurality of non-volatile memory cells, the method comprising:
performing a program operation of the plurality of non-volatile memory cells;
determining a program level of a least programmed memory cell of the plurality of non-volatile memory cells;
performing an erase operation of the plurality of non-volatile memory cells;
determining an erase level of a least erased memory cell of the plurality of non-volatile memory cells;
determining an operating window between the program level and the erase level; and
setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value.
2. The method of claim 1 , further comprising storing the program level, the erase level, and the read reference level.
3. The method of claim 2 , wherein storing the program level, the erase level, and the read reference level further comprises storing the program level, the erase level, and the read reference level in a protected portion of the plurality of non-volatile memory cells.
4. The method of claim 2 , wherein storing the program level, the erase level, and the read reference level further comprises storing the program level, the erase level, and the read reference level in a register file.
5. The method of claim 1 , wherein determining a program level of a least programmed memory cell further comprises determining a threshold voltage level of a least programmed memory cell of the plurality of memory cells.
6. The method of claim 1 , wherein determining a program level of a least programmed memory cell further comprises performing a program verify operation of the plurality of non-volatile memory cells while sweeping a word line voltage of a plurality of word lines for the plurality of non-volatile memory cells.
7. The method of claim 1 , wherein determining an erase level of a least erased memory cell of the plurality of memory cells further comprises performing an erase verify operation of the plurality of non-volatile memory cells while sweeping a word line voltage for the plurality of memory cells.
8. The method of claim 1 , wherein determining a read reference level for a plurality of non-volatile memory cells further comprises determining a read reference level for a plurality of thin film storage non-volatile memory cells.
9. The method of claim 8 , wherein the plurality of non-volatile memory cells comprises nanocrystals.
10. A memory comprising:
a plurality of non-volatile memory cells, each of the non-volatile memory cells coupled to a word line and a bit line, wherein when programmed, the plurality of non-volatile memory cells having a program level distribution, and when erased, the plurality of non-volatile memory cells having an erase level distribution;
a first register for storing a least programmed level of the program level distribution;
a second register for storing a least erased level of the erase level distribution;
a third register for storing a read reference level, wherein the read reference level is an offset level from the least erased level when a difference between the least programmed level and the least erased level compares favorably to a predetermined value; and
a controller circuit, coupled to the plurality of non-volatile memory cells, the controller circuit for controlling read operations to the plurality of non-volatile memory cells using the read reference level as a word line voltage.
11. The memory of claim 10 , wherein the plurality of non-volatile memory cells comprises a plurality of thin film storage non-volatile memory cells.
12. The memory of claim 10 , wherein each of the plurality of non-volatile memory cells has a charge storage layer comprising nanocrystals.
13. The memory of claim 10 , wherein the least programmed level and the least erased level are characterized as being a least programmed threshold voltage and a least erased threshold voltage, respectively.
14. The memory of claim 10 , the least programmed level and the least erased level are stored in a portion of the plurality of non-volatile memory cells.
15. The memory of claim 10 , further comprising:
a row decoder coupled to the controller circuit and to the word line; and
a read voltage regulator for providing the word line voltage to the row decoder in response to receiving the read reference level from the third register.
16. The memory of claim 10 , wherein the least programmed level and the least erased level are determined during production testing of the memory.
17. A memory comprising:
a memory array having a plurality of non-volatile memory cells, each of the non-volatile memory cells coupled to a word line and a bit line, wherein when programmed, the plurality of non-volatile memory cells having a program level distribution, and when erased, the plurality of non-volatile memory cells having an erase level distribution;
a first portion of the memory array for storing a least programmed level of the program level distribution;
a second portion of the memory array for storing a least erased level of the erase level distribution;
a third portion of the memory array for storing a read reference level, wherein the read reference level is an offset level from the least erased level when a difference between the least programmed level and the least erased level compares favorably to a predetermined value; and
a controller circuit, coupled to the plurality of non-volatile memory cells, the controller circuit for controlling read operations to the plurality of non-volatile memory cells using the read reference level as a word line voltage.
18. The memory of claim 17 , further comprising a first register of storing the least programmed level, a second register for storing the least erased level, and a third register for storing the read reference level.
19. The memory of claim 17 , further comprising:
a row decoder coupled to the controller circuit and to the word line; and
a read voltage regulator, the read voltage regulator for providing the word line voltage to a row decoder in response to receiving the read reference level.
20. The memory of claim 17 , wherein the plurality of non-volatile memory cells comprises a plurality of thin film storage non-volatile memory cells.