Monolithic microwave integrated circuit
View Patent ↗Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates ( 60 ) and lower resistance inductors ( 44′, 45 ′) for the IC ( 46 ). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors ( 44, 45 ) and interconnections ( 50 - 1′, 52 - 1′, 94, 94′, 94 ″) overlying the substrate ( 60 ). The active transistor(s) ( 41 ′) are formed in the substrate ( 60 ) proximate the front face ( 63 ). Planar capacitors ( 42′, 43 ′) are also formed over the front face ( 63 ) of the substrate ( 60 ). Various terminals ( 42 - 1′, 42 - 2′, 43 - 1, 43 - 2′,50′, 51′, 52′, 42 - 1′, 42 - 2 ′, etc.) of the transistor(s) ( 41 ′), capacitor(s) ( 42′, 43 ′) and inductor(s) ( 44′, 45 ′) are coupled to a ground plane ( 69 ) on the rear face ( 62 ) of the substrate ( 60 ) using through-substrate-vias ( 98, 98 ′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors ( 44′, 45 ′) and heavy current carrying conductors ( 52 - 1 ′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC ( 46, 58 ) previously unobtainable.
1. A monolithic microwave integrated circuit, comprising:
a semiconductor substrate having a bulk resistivity equal to or greater than about 100 Ohm-cm, and having a front surface and a rear surface;
at least one transistor in the semiconductor substrate and having an input terminal, an output terminal, a reference terminal, and a source region;
a dielectric layer formed over the front surface and overlying the source region;
at least one capacitor monolithically formed over the semiconductor substrate;
at least one inductor monolithically formed over the semiconductor substrate;
planar interconnections overlying the semiconductor substrate coupling the at least one transistor, capacitor, and inductor to form the monolithic integrated circuit;
a first conductive through-substrate via (TSV) extending through the dielectric layer and through the semiconductor substrate; and
an interlayer via formed in the first dielectric layer, the first conductive TSV electrically coupled to the source region of the transistor through the interlayer via.
2. The monolithic microwave integrated circuit of claim 1 , further comprising an input node thereof and an output node thereof, both supported by the front surface of the semiconductor substrate, and a reference node thereof supported by the rear surface of the semiconductor substrate.
3. The monolithic microwave integrated circuit of claim 2 , further comprising multiple conductive through-substrate vias in addition to the first conductive TSV, the multiple conductive through-substrate vias coupling one or more of the at least one transistor, the at least one capacitor and the at least one inductor to the reference node.
4. The monolithic microwave integrated circuit of claim 3 , wherein a first of the multiple conductive through-substrate vias couples the reference terminal of the at least one transistor to the reference node.
5. The monolithic microwave integrated circuit of claim 3 , wherein a second of the multiple through-substrate vias couples a first terminal of the at least one capacitor to the reference node.
6. The monolithic microwave integrated circuit of claim 2 , wherein the semiconductor substrate further comprises:
multiple conductive through-substrate vias in addition to the first conductive TSV, each of the multiple conductive through-substrate vias having a terminal coupled to the reference node;
two monolithic capacitors formed over the front surface of the semiconductor substrate, each having first and second terminals;
two monolithic inductors formed over the front surface of the semiconductor substrate, each having first and second terminals;
wherein the first terminal of the first capacitor is coupled to the first terminal of the first inductor and the second terminal of the first capacitor is coupled to a first of the multiple through substrate vias, and the second terminal of the first inductor is coupled to the input terminal of the transistor;
wherein the second capacitor and second inductor are serially coupled to form a combination, the combination having first and second terminals; and
wherein the first terminal of the combination is coupled to the output terminal of the at least one transistor and the second terminal of the combination is coupled to a second of the multiple conductive through-substrate vias.
7. The monolithic microwave integrated circuit of claim 1 , wherein the at least one capacitor is a planar capacitor, and wherein the at least one inductor is a planar inductor.
8. The monolithic microwave integrated circuit of claim 1 , wherein the at least one inductor comprises a high conductivity metal 0.1-10 micrometers thick.
9. A monolithic microwave integrated circuit having a circuit input terminal, a circuit output terminal and a circuit reference terminal, comprising:
a semiconductor substrate having a bulk resistivity equal to or greater than about 100 Ohm-cm, and having a front surface and a rear surface, wherein the rear surface has thereon the circuit reference terminal;
at least one Laterally-Diffused-Metal-Oxide-Semiconductor (LDMOS) transistor formed in the substrate and having a transistor input terminal, a transistor output terminal, a transistor reference terminal, a source region, and a body contact region laterally adjacent the source region, wherein the transistor reference terminal is coupled to the circuit reference terminal;
a first dielectric layer formed over the front surface;
at least first and second monolithic planar capacitors overlying the front surface;
at least first and second monolithic planar inductors overlying the front surface; and
at least one conductive through-substrate via electrically coupled to the source region and formed through the semiconductor substrate, through the body contact region of the at least one LDMOS transistor and through a region of the first dielectric layer overlying the body contact region;
wherein the first capacitor is coupled between the circuit input terminal and the circuit reference terminal, and the first inductor is coupled between the circuit input terminal and the transistor input terminal; and
wherein the second capacitor and the second inductor are coupled in series to form a combination, and a first terminal of the combination is coupled to the transistor output terminal and to the circuit output terminal and a second terminal of the combination is coupled to the circuit reference terminal.
10. The circuit of claim 9 , wherein the substrate substantially comprises float zone silicon.
11. The circuit of claim 9 , wherein at least one of the first and second inductors is formed from substantially high purity copper.
12. The circuit of claim 11 , wherein the high purity copper has a thickness of at least about 0.5 micrometers.
13. A monolithic microwave integrated circuit, comprising:
a semiconductor substrate having a front surface and a rear surface;
a transistor formed in the semiconductor substrate and including a source region;
an inductor monolithically formed over the semiconductor substrate;
planar interconnections overlying the front surface of the semiconductor substrate and coupling the transistor and inductor;
a reference node supported by the rear surface of the semiconductor substrate;
a first dielectric layer formed over the semiconductor substrate;
a first through-substrate via (“TSV”) extending through the first dielectric layer and the substrate to electrically couple the transistor to the reference node; and
an interlayer via formed in the first dielectric layer, the first TSV electrically coupled to the source region of the transistor through the interlayer via;
wherein the region of the semiconductor substrate through which the first TSV passes has a bulk resistivity equal to or greater than about 1000 Ohm-cm; and
wherein at least a portion of the inductor is formed over a region of the semiconductor substrate located adjacent the first TSV.
14. The monolithic microwave integrated circuit of claim 13 , further comprising a capacitor monolithically formed over the substrate and underlying at least a portion of the inductor.
15. The monolithic microwave integrated circuit of claim 13 , further comprising:
a first metal layer formed over the dielectric layer, the first TSV extending through the first dielectric layer to the first metal layer.
16. The monolithic microwave integrated circuit of claim 13 , wherein the transistor comprises a body contact region formed in the semiconductor substrate and having a dopant concentration less than the source region, the first TSV extending through the body contact region.
17. The monolithic microwave integrated circuit of claim 13 , further comprising a second TSV formed through the semiconductor substrate and laterally spaced from the first TSV, the transistor located substantially between the first TSV and the second TSV.
18. The monolithic microwave integrated circuit of claim 17 , wherein the transistor comprises a drain region formed in the semiconductor substrate, the transistor symmetrical about a centerline passing through the drain region and a portion of the inductor.
19. The monolithic microwave integrated circuit of claim 13 , wherein the transistor further comprises a body contact region formed in the substrate, wherein the monolithic microwave integrated circuit further comprises:
a conductor in ohmic contact with the source and body contact regions of the transistor, the interlayer conductive via electrically coupled between the first TSV and the conductor.
20. The monolithic microwave integrated circuit of claim 13 wherein the transistor comprises a Laterally-Diffused-Metal-Oxide-Semiconductor (LDMOS) transistor having a drain region, wherein the monolithic microwave integrated circuit further comprises a drain contact region in ohmic contact with the drain region, and wherein the interlayer conductive via is located laterally between the drain contact region and the first TSV.