IP Library Granted Patent US 8,138,073
Granted Patent B2
US 8,138,073 · App. 12/766,395 · Granted Mar 20, 2012

Method for forming a Schottky diode having a metal-semiconductor Schottky contact

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Quick Facts
Patent No.
US 8,138,073
App. No.
12/766,395
Granted
Mar 20, 2012
Kind
B2
Abstract

A method for forming a metal-semiconductor Schottky contact in a well region is provided. The method includes forming a first insulating layer overlying a shallow trench isolation in the well region; and removing a portion of the first insulating layer such that only the well region and a portion of the shallow trench isolation is covered by a remaining portion of the first insulating layer. The method further includes forming a second insulating layer overlying the remaining portion of the first insulating layer and using a contact mask, forming a contact opening in the second insulating layer and the remaining portion of the first insulating layer to expose a portion of the well region. The method further includes forming the metal-semiconductor Schottky contact in the exposed portion of the well region by forming a metal layer in the contact opening and annealing the metal layer.

Claims (60)

1. A method for forming a metal-semiconductor Schottky contact in a well region, the method comprising:

forming shallow trench isolation in the well region to form a first well region separated from a second well region by the shallow trench isolation;

forming a first insulating layer overlying the shallow trench isolation, the first well region, and the second well region;

removing a portion of the first insulating layer such that only the first well region and a portion of the shallow trench isolation is covered by a remaining portion of the first insulating layer;

forming a highly doped region in the second well region;

siliciding a top portion of the highly doped region to form a silicide layer;

forming a second insulating layer overlying the remaining portion of the first insulating layer and the silicide layer;

using a contact mask, forming a contact opening in the second insulating layer and the remaining portion of the first insulating layer to expose a portion of the first well region; and

forming the metal-semiconductor Schottky contact in the exposed portion of the first well region by forming a metal layer in at least a portion of the contact opening and annealing the metal layer.

2. The method of claim 1 , wherein the metal-semiconductor Schottky contact opening has a first area and the first well region has a second area, and wherein the first area is smaller than the second area.

3. The method of claim 1 further comprising:

prior to forming the first insulating layer, forming a gate dielectric layer overlying the first well region and the second well region;

removing a portion of the gate dielectric layer such that only the first well region and the portion of the shallow trench isolation is covered by a remaining portion of the gate dielectric layer; and

using the contact mask, forming the contact opening in the gate dielectric layer to expose the portion of the first well region.

4. The method of claim 1 further comprising:

using the contact mask, forming a second contact opening in the second insulating layer to expose a portion of the silicide layer.

5. The method of claim 1 further comprising:

forming a contact plug in the contact opening by filling the contact opening with a conductive material.

6. The method of claim 1 , wherein the metal layer comprises titanium and wherein the step of forming the metal-semiconductor Schottky contact comprises one of collimated sputtering or ionized metal plasma deposition process to form the metal layer in the contact opening.

7. The method of claim 1 further comprising:

prior to siliciding the top portion of the highly doped region, annealing the second well region.

8. A method for forming a Schottky diode in a well region, the method comprising:

forming shallow trench isolation in the well region to form a first well region separated from a second well region by the shallow trench isolation;

forming a gate dielectric layer overlying the first well region and second well region;

forming a first insulating layer overlying the gate dielectric layer;

removing a portion of the first insulating layer and a portion of the gate dielectric layer such that only the first well region and a portion of the shallow trench isolation is covered by a remaining portion of the first insulating layer and a remaining portion of the gate dielectric layer;

forming a highly doped region in the second well region;

siliciding a top portion of the highly doped region to form a silicide layer;

forming a second insulating layer overlying the remaining portion of the first insulating layer and the silicide layer;

using a contact mask, forming a contact opening in the second insulating layer, the remaining portion of the first insulating layer, and the remaining portion of the gate dielectric layer to expose a portion of the first well region;

forming a metal-semiconductor Schottky contact in the exposed portion of the first well region by forming a metal layer in at least a portion of the contact opening and annealing the metal layer such that the Schottky diode is formed with the metal-semiconductor Schottky contact as an anode and the highly doped region as a cathode.

9. The method of claim 8 , wherein the metal-semiconductor Schottky contact has a first area and the first well region has a second area, and wherein the first area is smaller than the second area.

10. The method of claim 8 further comprising:

using the contact mask, forming a second contact opening in the second insulating layer to expose a portion of the silicide layer.

11. The method of claim 8 further comprising:

forming a contact plug in the contact opening by filling the contact opening with a conductive material.

12. The method of claim 8 , wherein the metal layer comprises titanium and wherein the step of forming the metal-semiconductor Schottky contact comprises using one of collimated sputtering or ionized metal plasma deposition to form the metal layer in the contact opening.

13. The method of claim 8 further comprising:

prior to siliciding the top portion of the highly doped region, annealing the second well region.

14. A method for forming a titanium-silicon Schottky contact in a well region, wherein the well region comprises silicon, the method comprising:

forming shallow trench isolation in the well region to form a first well region separated from a second well region by the shallow trench isolation;

forming a first insulating layer overlying the shallow trench isolation, the first well region, and the second well region;

removing a portion of the first insulating layer such that only the first well region and a portion of the shallow trench isolation is covered by a remaining portion of the first insulating layer;

forming a highly doped region in the second well region;

siliciding a top portion of the highly doped region to form a silicide layer;

forming a second insulating layer overlying the remaining portion of the first insulating layer and the silicide layer;

using a contact mask, forming a contact opening in the second insulating layer and the remaining portion of the first insulating layer to expose a portion of the first well region; and

forming the titanium-silicon Schottky contact in the exposed portion of the first well region by using a titanium layer and a titanium-nitride layer in at least a portion of the contact opening and annealing the titanium layer and the titanium-nitride at a predetermined temperature for at least a predetermined duration selected to obtain a low resistance at the titanium-silicon Schottky contact.

15. The method of claim 14 , wherein the titanium-silicon Schottky contact has a first area and the first well region has a second area, and wherein the first area is smaller than the second area.

16. The method of claim 14 further comprising:

prior to forming the first insulating layer, forming a gate dielectric layer overlying the first well region and the second well region;

removing a portion of the gate dielectric layer such that only the first well region and the portion of the shallow trench isolation is covered by a remaining portion of the gate dielectric layer; and

using the contact mask, forming the contact opening in the gate dielectric layer to expose the portion of the first well region.

17. The method of claim 14 further comprising:

using the contact mask, forming a second contact opening in the second insulating layer to expose a portion of the silicide layer.

18. The method of claim 14 further comprising:

forming a contact plug in the contact opening by filling the contact opening with a conductive material.

19. The method of claim 14 , wherein the step of forming the titanium-silicon Schottky contact comprises using one of collimated sputtering or ionized metal plasma deposition to form the titanium layer in the contact opening.

20. The method of claim 14 further comprising:

prior to siliciding the top portion of the highly doped region, annealing the second well region.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2010
From: TRIVEDI, VISHAL P.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 024281/0437 →