Granted Patent B2

US 8,543,856 · App. 13/214,164 · Granted Sep 24, 2013

Abstract

Claims (13)

1. A semiconductor device having a plurality of I/O pads, wherein the semiconductor device is operable in a low power mode, the semiconductor device comprising:

at least one interface pad;

a buffer circuit connected to the interface pad, wherein the buffer circuit includes,

an input buffer having an input terminal connected to the interface pad for receiving a signal input to the interface pad,

an output buffer having an output terminal connected to the interface pad and the input terminal of the input buffer, for transmitting a signal to the interface pad, and

a resistor having a first terminal connected to the interface pad, the input terminal of the input buffer, and the output terminal of the output buffer, and a second terminal for providing a wake-up signal;

a power management controller (PMC) coupled to said I/O pads and said interface pad for supplying power thereto, wherein power to said I/O pads and said interface pad is disabled during said low power mode by assertion of a power on reset signal of said PMC;

a first level shifter, connected to the second terminal of the resistor of the buffer circuit, for receiving the wake-up signal and shifting a voltage level of the wake-up signal from a analog supply high operation voltage level to a core operation voltage level; and

a wake-up unit connected to the first level shifter for receiving the level-shifted wake-up signal, wherein the wake-up unit wakes up at least a part of said semiconductor device from said low power mode.

2. The semiconductor device of claim 1 , further comprising:

a memory for storing package personality data including I/O pad usage data;

a second level shifter connected to the memory for shifting an output of the memory from a low voltage level to a high voltage level; and

a logic gate connected between the first level shifter and the buffer circuit, wherein the logic gate has a first input terminal that receives the wake-up signal and a second input connected to the second level shifter for receiving the level shifted memory output, and an output terminal connected to an the input of the first level shifter.

Assignments (31)