Double edge triggered flip flop
View Patent ↗A dual edge triggered flip flop circuit uses clock signals that are delayed from a first clock signal and from one another by respective intervals. A first set of the plurality of clock signals are used to operate a first latch circuit to allow first data to be conducted to a storage element for a period of time after a rising edge of a first clock signal. The clock signals are further used to operate a second latch circuit to allow second data to be conducted to the storage element for a period of time after a falling edge of the first clock signal.
1. A dual edge triggered flip flop circuit, comprising:
a single storage element;
a first latch circuit and a second latch circuit coupled to alternate input to the single storage element between a first feedback path and a second feedback path on rising and falling edges of a first clock signal; and
a clock signal generator configured to receive the first clock signal and to output a plurality of clock signals including a first inverted clock signal, a second clock signal, and a second inverted clock signal, wherein the plurality of clock signals are delayed from one another and from the first clock signal by respective specified intervals; and
wherein:
the first latch circuit is in a conducting state and the second latch circuit is in a non-conducting state for a first window of time at the rising edge of the first clock signal; and
the second latch circuit is in a conducting state and the first latch circuit is in a non-conducting state for a second window of time at the falling edge of the first clock signal.
2. The dual edge triggered flip flop circuit of claim 1 , wherein:
the first latch circuit includes a first transmission gate, a second transmission gate, and a third transmission gate;
an input to the third transmission gate is coupled to receive a data signal and operation of the third transmission gate is controlled by the second clock signal and the second inverted clock signal;
an output of the third transmission gate is coupled to inputs of the first transmission gate and the second transmission gate;
operation of the first transmission gate is controlled by the second clock signal and the first inverted clock signal; and
operation of the second transmission gate is controlled by the second clock signal and the first inverted clock signal.
3. The dual edge triggered flip flop circuit of claim 2 further wherein:
the second latch circuit includes a first transmission gate, a second transmission gate, and a third transmission gate;
an input to the third transmission gate is coupled to receive the data signal and operation of the third transmission gate is controlled by the second clock signal and the second inverted second clock signal;
an output of the third transmission gate is coupled to inputs of the first transmission gate and the second transmission gate;
operation of the first transmission gate is controlled by the second clock signal and the first inverted clock signal; and
operation of the second transmission gate is controlled by the second clock signal and the first inverted clock signal.
4. The dual edge triggered flip flop circuit of claim 1 , wherein:
the single storage element includes an AND-OR-Invert circuit; and
the first latch circuit includes a first transmission gate and a second transmission gate;
an input to the first transmission gate is coupled to receive a data signal;
an output of the first transmission gate is coupled to a first input of the AND-OR-Invert circuit;
an input to the second transmission gate is coupled to receive a feedback signal from the single storage element; and
an output of the second transmission gate is coupled between the first transmission gate and the first input of the AND-OR-Invert circuit.
5. The dual edge triggered flip flop circuit of claim 4 , wherein:
the second latch circuit includes a first transmission gate and a second transmission gate;
an input to the first transmission gate is coupled to receive the data signal,
an output of the first transmission gate is coupled to a second input of the AND-OR-Invert circuit,
an input to the second transmission gate is coupled to receive the feedback signal from the single storage element; and
an output of the second transmission gate is coupled to the second input of the AND-OR-Invert circuit.
6. The dual edge triggered flip flop circuit of claim 5 , wherein:
the first clock signal and the first inverted first clock signal are coupled to control operation of the AND-OR-Invert circuit; and
the second clock signal and the second inverted clock signal are coupled to control operation of the first and second transmission gates of the first and second latch circuits.
7. A dual edge triggered flip flop circuit comprising:
a storage element shared between a first latch circuit and a second latch circuit;
a clock signal generator configured to receive a first clock signal and to output a plurality of clock signals including a first inverted clock signal, a second clock signal, and a second inverted clock signal, wherein the plurality of clock signals are delayed from one another and from the first clock signal by respective specified intervals;
the first latch circuit includes a first transmission gate controlled by the second clock signal and the second inverted clock signal to allow input of first data to the storage element during a period of time after a rising edge of the first clock signal; and
the second latch circuit includes a first transmission gate controlled by the second clock signal and the second inverted clock signal in polarity opposite to the first transmission gate of the first latch circuit to allow input of second data to the storage element during a period of time after the falling edge of the first clock signal;
wherein the first latch circuit further includes a second transmission gate and a third transmission gate, the second and third transmission gates of the first latch circuit comprise a P-MOS switch controlled by the first inverted clock signal and a N-MOS switch controlled by the second clock signal.
8. The dual edge triggered flip flop circuit of claim 7 wherein:
the second latch circuit further includes a second transmission gate and a third transmission gate, the second and third transmission gates of the second latch circuit comprise a P-MOS switch controlled by the second clock signal and a N-MOS switch controlled by the first inverted clock signal.
9. The dual edge triggered flip flop circuit of claim 8 wherein:
the storage element includes a first inverter and a second inverter, in the first latch circuit:
an output of the second transmission gate is coupled to an input of the first inverter;
an output of the first inverter is coupled to an input of the second inverter;
an output of the second inverter is coupled to an input of the third transmission gate;
an output of the third transmission gate is coupled to an input of the second transmission gate;
an output of the first transmission gate is coupled between the output of the third transmission gate and the input of the second transmission gate; and
an input to the first transmission gate is coupled to receive first and second data.
10. The dual edge triggered flip flop circuit of claim 9 wherein:
in the second latch circuit:
an output of the second transmission gate is coupled to the input of the first inverter;
the output of the first inverter is coupled to the input of the second inverter,
the output of the second inverter is coupled to an input of the third transmission gate;
an output of the third transmission gate is coupled to an input of the second transmission gate;
an output of the first transmission gate is coupled between the output of the third transmission gate and the input of the second transmission gate; and
the input of the first transmission gate in the first latch circuit is coupled to the input of the first transmission gate in the second latch circuit.
11. The dual edge triggered flip flop circuit of claim 7 wherein:
the first latch circuit further includes a second transmission gate comprising a P-MOS switch controlled by the second inverted clock signal and a N-MOS switch controlled by the second clock signal; and
the second latch circuit further includes a second transmission gate comprising a P-MOS switch controlled by the second inverted clock signal and a N-MOS switch controlled by the second clock signal.
12. The dual edge triggered flip flop circuit of claim 11 wherein:
the storage element includes an AND-OR-Invert circuit;
in the first latch circuit:
an input to the first transmission gate is coupled to receive the first and second data;
an output of the first transmission gate is coupled to a first input of the AND-OR-Invert circuit;
an input to the second transmission gate is coupled to receive a feedback signal from the storage element; and
an output of the second transmission gate is coupled between the first transmission gate and the first input of the AND-OR-Invert circuit; and
in the second latch circuit:
an input to the first transmission gate is coupled to receive a data signal;
an output of the first transmission gate is coupled to a second input of the AND-OR-Invert circuit;
an input to the second transmission gate is coupled to receive the feedback signal from the storage element; and
an output of the second transmission gate is coupled to the second input of the AND-OR-Invert circuit.
13. The dual edge triggered flip flop circuit of claim 12 wherein:
the second transmission gate of the first latch circuit and the first transmission gate of the second latch circuit include a N-MOS switch controlled by the second clock signal and a P-MOS switch controlled by the second inverted clock signal;
the first transmission gate of the first latch circuit and the second transmission gate of the second latch circuit include a N-MOS switch controlled by the second inverted clock signal and a P-MOS switch controlled by the second clock signal; and
the first clock signal and the first inverted clock signal are coupled to control operation of the AND-OR-Invert circuit.
14. The dual edge triggered flip flop circuit of claim 7 wherein:
the storage element includes an AND-OR-Invert circuit;
the first latch circuit further includes a second transmission gate comprising a P-MOS switch controlled by the second clock signal and a N-MOS switch controlled by the second inverted clock signal;
the second latch circuit further includes a second transmission gate comprising a P-MOS switch controlled by the second inverted clock signal and a N-MOS switch controlled by the second clock signal; and
the first clock signal and the first inverted clock signal are coupled to control operation of the AND-OR-Invert circuit.