Method for manufacturing a semiconductor device and semiconductor device obtainable with such a method
View Patent ↗A method for manufacturing a semiconductor device includes providing a patterned hard-mask layer. The hard-mask layer is provided on an exposed surface of one or more layers to be patterned of a semiconductor intermediate product. The hard-mask layer covers the exposed surface in covered areas of the one or more layers to be patterned and does not cover the exposed surface in bared areas of the one or more layers to be patterned. One or more recesses are formed in the layers to be patterned by at least partially removing the layers to be patterned in the bared areas. The hard-mask layer is ten removed. After removing the hard-mask layer the recess is filled with a filling material.
1. A method for manufacturing a semiconductor device, comprising:
providing, on an exposed surface of at least one layer to be patterned of a semiconductor intermediate product, a patterned hard-mask layer of a metal or metal compound which covers the exposed surface in covered areas of said at least one layers to be patterned and which patterned hard-mask layer does not cover said exposed surface in bared areas of said at least one layers to be patterned;
forming at least one recess in said at least one layers to be patterned by at least partially removing said at least one layers to be patterned in the bared areas;
removing the hard-mask layer using a wet-etchant containing peroxide; and
filling said recess with a filling material after removing the hard-mask layer.
2. A method as claimed in claim 1 , wherein the wet-etchant is heated.
3. A method as claimed in claim 2 , wherein the wet-etchant contains 28 volume % of NH4OH and/or 37 volume % of HCI and/or 30 volume of peroxide.
4. A method as claimed in claim 1 , wherein the wet-etchant is a wet-etchant containing H2O and one or more of NH4OH and HCI, such as SC1 or SC2.
5. A method as claimed in claim 1 , wherein the wet-etchant contains 28 volume % of NH4OH and/or 37 volume % of HCI and/or 30 volume % of peroxide.
6. A method as claimed in claim 5 , including removing a barrier layer positioned below the layer to be patterned after removing said hard mask layer at least where said barrier layer lies bare after said forming of said recess, said barrier layer protecting the material below the barrier layer against undesired etching.
7. A method as claimed in claim 1 , wherein the wet-etchant contains a dissolution of peroxide, organic residuals, inorganic salts, fluorine salts, corrosion inhibitors, metal complexants, buffers, surfactants and 2-(2-butoxyethoxy)ethanol.
8. A method as claimed in claim 1 , wherein the hard-mask layer is made of aluminium, copper, titanium, tantalum, tungsten or analogues, mixtures, compounds and/or alloys thereof.
9. A method as claimed in claim 1 , wherein the hard-mask layer is made of a metal-nitride, such as TiN, TaN or HfN, or analogues, mixtures, compounds and/or alloys thereof.
10. A method as claimed in claim 1 , further comprising;
processing, after filling said recess with a filling material, the semiconductor intermediate product to obtain a semiconductor device.
11. A method as claimed in claim 1 , wherein said dielectric layer is a low-k dielectric layer with a dielectric constant of 2.5 or lower.
12. A method as claimed in claim 11 , wherein said dielectric material is a porous material.
13. A method as claimed in claim 1 , wherein said dielectric material is a porous material.
14. A method as claimed in claim 1 , including removing a barrier layer positioned below the layer to be patterned after removing said hard mask layer at least where said barrier layer lies bare after said forming of said recess, said barrier layer protecting the material below the barrier layer against undesired etching.
15. A method as claimed in claim 1 , wherein said barrier layer is made of a barrier metal of the group consisting of: Co, W, P, Ni, Mo, Pd, Sn, In, Mg, Al, Zr, Ce, Ir or oxides and/or mixtures, compounds or alloys thereof.
16. A method as claimed in claim 14 , wherein said material below the barrier layer is copper, aluminium, silver, gold or tungsten or mixtures, compounds or alloys including such materials.
17. A method as claimed in claim 14 , wherein the barrier layer is removed after application of a cleaning agent to walls of the recess, for removing contaminants.
18. A method as claimed in claim 1 , wherein the wet-etchant is heated to 90° C. or above.
19. A method as claimed in claim 1 , wherein said dielectric layer is a low-k dielectric layer with a dielectric constant of 2.2 or lower.
20. A semiconductor device manufactured by a method comprising:
providing, on an exposed surface of at least one layer to be patterned of a semiconductor intermediate product, a patterned hard-mask layer of a metal or metal compound which covers the exposed surface in covered areas of said at least one layers to be patterned and which patterned hard-mask layer does not cover said exposed surface in bared areas of said at least one layers to be patterned;
forming at least one recess in said at least one layers to be patterned by at least partially removing said at least one layers to be patterned in the bared areas;
removing the hard-mask layer using a wet-etchant containing peroxide; and
filling said recess with a filling material after removing the hard-mask layer.