Method for reducing surface area of pad limited semiconductor die layout
View Patent ↗A method for reducing a surface area of a pad limited semiconductor die layout includes choosing an outer die pad row from a group of outer die pad rows on the semiconductor die, each of the outer die pad rows being adjacent an edge of the semiconductor die. Next, the method performs selecting, from the outer die pad row, a common die pad group with die pads that are arranged to be electrically connected to an external connection pad. The method then performs repositioning a subgroup of the common die pad group on an inner die pad row, the inner pad row being adjacent the outer die pad row. After he repositioning there is performed a step of adjusting positions of at least some of the remaining pads in the outer die pad row thereby reducing an overall length of the outer die pad row. The method then provides for repeating the above steps until the surface area of a pad limited semiconductor die cannot be reduced any further by the step of adjusting positions or until every common die pad group, on every one of the outer die pad rows, has been selected by the selecting step.
1. A method for reducing a surface area of a pad limited semiconductor die, the method comprising:
choosing an outer die pad row from a group of outer die pad rows on the semiconductor die, each of the outer die pad rows being adjacent an edge of the semiconductor die;
selecting, from the chosen outer die pad row, a common die pad group with die pads that are arranged to be electrically connected to a single external connection pad;
repositioning a subgroup of the common die pad group on an inner die pad row, the inner pad row being adjacent the outer die pad row, wherein the die pads of the common die pad group are positioned with respect to each other such that a bond wire connecting the die pads of the common die pad group to the external connection pad have a spacing less than a minimum defined bond wire spacing for the semiconductor device;
adjusting positions of at least some of the remaining pads in the outer die pad row thereby reducing an overall length of the outer die pad row;
repeating the above steps until the surface area of a pad limited semiconductor die cannot be reduced any further by the step of adjusting positions or until every common die pad group, on all of the outer die pad rows, has been selected by the selecting step; and
fabricating the semiconductor die with the reduced overall length of the outer die pad row.
2. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein the choosing an outer die pad row includes choosing a longest outer die pad row from the group of die pad rows.
3. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein the selecting prioritizes the selecting of a common die pad group comprising the most die pads.
4. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein the common die pad group comprises power supply die pads.
5. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein the common die pad group comprises signal or data die pads.
6. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein the repositioning is characterized by the subgroup of the common die pad group including all but one of the common die pad group.
7. The method for reducing a surface area of a pad limited semiconductor die of claim 6 , wherein the repositioning is further characterized by the subgroup being positioned adjacent the common die pad remaining in the outer row.
8. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein the adjusting positions is characterized by maintaining a minimum bond wire pitch spacing between each of the die pads in the outer die pad row.
9. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , the method including a further step of adjusting pad rail lengths on the semiconductor die to conform with the reduced overall lengths of one or more die pad rows.
10. The method for reducing a surface area of a pad limited semiconductor die of claim 9 , wherein the adjusting pad rail lengths on the semiconductor die is characterized by the pad rails lengths being aligned under respective outer die pad rows.
11. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein there is an outer die pad row adjacent each edge of the semiconductor die layout.
12. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein there is an outer die pad row adjacent each two opposite edges of the semiconductor die layout.
13. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein when it is determined that the surface area of the pad limited semiconductor die cannot be reduced any further by comparing a core limited area of the semiconductor die with a pad limited area of the semiconductor die, then the pad limited area is determined after the step of adjusting.
14. The method for reducing a surface area of a pad limited semiconductor die of claim 13 , wherein the pad limited area is determined, after each repetition of the step of adjusting, by the lengths of the outer die pad rows.
15. The method for reducing a surface area of a pad limited semiconductor die of claim 14 , wherein the pad limited area is determined by the minimum semiconductor die periphery required to accommodate the outer die pad rows.
16. The method for reducing a surface area of a pad limited semiconductor die of claim 14 , wherein the core limited area is determined by an area of the semiconductor die allocated to core circuitry.
17. The method for reducing a surface area of a pad limited semiconductor die of claim 14 , wherein the core limited area is determined by adding an area of the semiconductor die allocated to core circuitry with one or more areas allocated to each subgroup on an inner pad row.
18. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein the repositioning includes modifying a shape of a core area of the semiconductor die layout.
19. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein the adjusting positions includes modifying a shape of a core area of the semiconductor die layout.
20. The method for reducing a surface area of a pad limited semiconductor die of claim 1 , wherein the adjusting positions includes adjusting positions of pads of subgroup on the inner die pad row in order to meet a minimum bond wire pitch spacing between each of the die pads on the outer die pad row.