System and method to improve switching in power switching applications
View Patent ↗A circuit for improving the control of a change in state of a signal in an electronic device between a first state and a second state, wherein a first change in state occurs when the state changes from the second state to the first state and a second change in state occurs when the state changes from the first state to the second state and wherein the first and second changes in state have associated therewith a first and a second time delay over which each change in state occurs, characterized in that said circuit comprises a determining unit for measuring the first time delay and a calculator for calculating a common delay to replace one or more of the first and second delays to thereby improve the control of the change in state of the signal.
1. A PWM circuit for controlling a change in state of a signal applied to a power transistor in an electronic device between a first OFF state and a second ON state, wherein a first change in state occurs when the state changes from the second ON state to the first OFF state and a second change in state occurs when the state changes from the first OFF state to the second ON state and wherein the first change in state has associated therewith a first time delay over which the first change in state occurs, the circuit comprises:
a control unit for applying an instruction to the electronic device for triggering the change in state;
a determining unit for measuring the first time delay; and
a calculation module for calculating a time lag based on the first time delay and delaying the triggering of the second change in state by the time lag.
2. A circuit as claimed in claim 1 , wherein the calculation module compares a characteristic voltage of the electronic device and a predetermined threshold value to determine the first time delay.
3. A circuit as claimed in claim 2 wherein the second change in state has associated therewith a second time delay over which the second change in state occurs, and the determining unit further measures the second time delay; and the calculation module for calculating the time lag based on a difference between the first time delay and the second time delay and determining either the first or the second time delay as a shortest time delay and delaying the triggering of the second change in state by the time lag when the first time delay is the shortest delay and delaying the triggering of the first change in state by the time lag when the second time delay is the shortest delay.
4. A circuit as claimed in claim 1 wherein the second change in state has associated therewith a second time delay over which the second change in state occurs, and the determining unit further measures the second time delay; and the calculation module for calculating the time lag based on a difference between the first time delay and the second time delay and determining either the first or the second change in state by the time lag when the first time delay is the shortest delay and delaying the triggering of the first change in state by the time lag when the second time delay is the shortest delay.
5. A circuit as claimed in claim 1 , wherein the first change in state comprises a saturation phase and the first time delay corresponds to a duration of the saturation phase.
6. A circuit as claimed in claim 5 , wherein the determining unit measures the first time delay when the electronic device is switched ON.
7. A circuit as claimed in claim 1 , wherein the determining unit measures the first time delay when the electronic device is switched OFF.
8. A circuit as claimed in claim 1 , wherein the circuit operates in a high duty cycle between about 95% and 100%.
9. A circuit as claimed in claim 1 , wherein the circuit operates in a low duty cycle between about 0% and 5%.
10. A system comprising the circuit according to claim 1 , wherein the electronic device comprises an LED lighting device.
11. A circuit as claimed in claim 1 wherein the circuit operates in a low duty cycle between about 0% and 5%.
12. A method for controlling a change in state of a signal in an electronic device between a first OFF state and a second ON state, wherein a first change in state occurs when the state changes from the second ON state to the first OFF state and a second change in state occurs when the state changes from the first OFF state to the second ON state and wherein the first change in state has associated therewith a first time delay over which the first change in state occurs, said method comprising:
determining the first time delay associated with the first change in state;
calculating a time lag based on the first time delay; and
delaying a triggering of the second change in state by the time lag.
13. A method as claimed in claim 12 , further comprising
determining a second time delay associated with the second change in state;
calculating the time lag based on a difference between the first time delay and the second time delay and determining either the first or the second time delay as a shortest delay;
delaying the triggering of the second change in state by the time lag when the first time delay is the shortest delay and delaying the triggering of the first change in state by the time lag when the second time delay is the shortest delay.
14. A method as claimed in claim 13 , further comprising running the electronic device in a high duty cycle between about 95% and 100%.
15. A method as claimed in claim 13 , further comprising running the electronic device in a low duty cycle between about 0% and 5%.
16. A method as claimed in claim 12 , further comprising running the electronic device in a high duty cycle between about 95% and 100%.
17. A method as claimed in claim 12 , further comprising running the electronic device in a low duty cycle between about 0% and 5%.
18. A non-transitory computer readable medium including a computer program comprising instructions to carry out a control of a change in state of a signal in an electronic device between a first OFF state and a second ON state, wherein a first change in state occurs when the state changes from the second ON state to the first OFF state and a second change in state occurs when the state changes from the first OFF state to the second ON state and wherein the first change in state has associated therewith a first time delay over which the first change in state occurs, said instructions comprise:
determining the first time delay associated with the first change in state;
calculating a time lag based on the first time delay and
delaying a triggering of the second change in state by the time lag.