Granted Patent B2

US 8,504,777 · App. 12/886,641 · Granted Aug 6, 2013

Abstract

Claims (42)

1. A method of operating a data processing system including a data processor and a memory, the method comprising:

issuing a data processing instruction by the data processor;

determining if the data processing instruction is a decorated access instruction with cache bypass;

determining if the data processing instruction generates a cache hit to a cache; and

when the data processing instruction is determined to be a decorated access instruction with cache bypass and the data processing instruction is determined to generate a cache hit, the method further comprising:

invalidating a cache entry of the cache associated with the cache hit; and

performing by a memory controller of the memory, a decoration operation specified by the data processor instruction on a location in the memory designated by a target address of the data processor instruction, wherein the performing the decorated access includes the memory controller performing a read of a value of the location in memory, modifying the value to generate a modified value, and writing the modified value to the location.

2. The method of claim 1 wherein when the data processing instruction is determined not to be a decorated access instruction with cache bypass and the data processor instruction is determined to generate a cache hit, performing an operation specified by the data processing instruction on the cache entry.

3. The method of claim 1 wherein the determining if the data processing instruction is a decorated access instruction with cache bypass includes determining whether the data processing instruction is of a decorated access instruction type characterized as a decorated access instruction with cache bypass, wherein not all decorated access instruction types issued by the data processor are characterized as a decorated access instruction with cache bypass.

4. The method of claim 1 wherein the determining if the data processing instruction is a decorated access instruction with cache bypass is made by determining if the data processing instruction is a decorated access instruction, wherein all decorated access instructions issued by the data processor are decoration access instructions with cache bypass.

5. The method of claim 1 wherein:

when the data processing instruction is determined not to be a decorated access instruction with cache bypass and the data processing instruction is determined not to generate a cache hit, the method further comprising:

performing an operation specified by the data processor instruction on a location in the memory designated by a target address of the data processor instruction, wherein the performing includes storing a first value in the memory location; and

storing the first value in a first cache entry of the cache; and

when the instruction is determined to be a decorated access instruction with cache bypass and the data processing instruction is determined to generate a cache hit, the modified value is not stored in the cache entry.

6. The method of claim 1 wherein when the data processing instruction is determined to be a decorated access instruction with cache bypass and the data processing instruction is determined to generate a cache hit, the modified value is not stored in the cache entry.

7. The method of claim 1 wherein the location in memory is designated as cacheable by the data processor.

8. The method of claim 1 wherein the location in memory is located in a page of the memory, wherein the page of the memory is designated as cacheable by the data processor.

9. The method of claim 8 wherein the page of memory is designated as having a copyback attribute by the data processor, wherein the decorated access instruction with cache bypass performs a write-through access to the location in memory.

10. The method of claim 1 wherein the data processor includes a load store unit, the load store unit providing to the cache an indication that the data processor instruction is a decorated access instruction with cache bypass when the data processor instruction is determined to be a decorated access instruction with cache bypass.

11. The method of claim 1 wherein the data processor includes a instruction decoder, wherein the determining if the data processing instruction is a decorated access instruction with cache bypass is performed by the instruction decoder.

12. The method of claim 11 wherein:

the data processor includes a load store unit;

the method further comprising:

providing by the instruction decoder an indication that the data processor instruction is a decorated access instruction with cache bypass when the data processor instruction is determined to be a decorated access instruction with cache bypass; and

receiving by the load store unit the indication and providing by the load store unit the indication to the cache when the data processor instruction is determined to be a decorated access instruction with cache bypass.

13. The method of claim 1 wherein when the data processing instruction is determined to be a decorated access instruction with cache bypass and the data processing instruction is determined to generate a cache hit, the method further comprising flushing the cache entry of the cache associated with the cache hit.

14. The method of claim 1 wherein the flushing the cache entry of the cache associated with the cache hit includes:

determining if the cache entry is coherent with the location in memory;

when the cache entry is determined not to be coherent, writing a data value of the cache entry to the location in the memory before the memory controller performs the read of the value of the location in memory;

wherein when the cache entry is determined to be coherent, the data value is not written to the location in memory.

15. The method of claim 1 further comprising:

receiving by the data processor, the modified value, wherein the modified value is not stored in the cache entry.

16. A data processor comprising:

an instruction decoder, the instruction decoder for decoding processor instructions including decorated access instructions;

an interface circuit operable for coupling to a system interconnect; and

a cache, the cache including a plurality of cache entries and a cache controller, the cache controller in response to receiving a data processor instruction, determines if a target address of the data processor instruction generates a cache hit in a cache entry of the plurality of cache entries, wherein when the data processor instruction is determined to be a decorated access instruction with cache bypass, the cache controller invalidates the cache entry and the decorated access instruction is provided to a system interconnect by the interface circuit for performance by a memory controller of a memory of a decoration operation specified by the data processor instruction on a location in the memory designated by the target address.

17. The data processor of claim 16 wherein when a data processor instruction is determined to be a decorated access instruction with cache bypass, the cache controller cache flushes a cache entry corresponding to a cache hit generated by the data processor instruction.

18. The data processor of claim 16 wherein when a data processor instruction is determined not to be a decorated access instruction with cache bypass, the cache controller performs an operation specified by the data processor instruction on the cache entry corresponding to a cache hit generated by a data processor instruction.

19. The data processor of claim 16 wherein the instruction decoder determines whether a data processor instruction is a decorated access instruction with cache bypass.

20. The data processor of claim 16 further comprising:

a load store unit, the cache receives an indication of whether a data processor instruction is a decorated access instruction with cache bypass from the load store unit.

Assignments (23)