Transistors with immersed contacts
View Patent ↗Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region.
1. A semiconductor device comprising:
a gate structure; and
a first contact, wherein the first contact extends into the gate structure and is electrically coupled to the gate structure, and sidewalls of the first contact are completely surrounded by the gate structure.
2. A semiconductor device comprising:
a semiconductor structure on a substrate, wherein the semiconductor structure comprises a first current electrode region, a second current electrode region, and a fin structure between the first current electrode region and the second current electrode region, wherein a channel region is located in the fin structure, and a carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region;
a gate structure formed over the fin structure and the substrate; and
a first contact within the gate structure, wherein sidewalls of the first contact are completely surrounded by the gate structure, and wherein the first contact is electrically coupled to the gate structure.
3. The semiconductor device of claim 2 , further comprising:
a second contact within the first current electrode region, wherein sidewalls of the second contact are completely surrounded by the first current electrode region, and the second contact is electrically coupled to the first current electrode region.
4. The semiconductor device of claim 2 , wherein the first contact is formed in an opening defined by a sidewall of the gate structure, and the device further comprises:
a silicide between the first contact and the sidewall of the gate structure.
5. The semiconductor device of claim 2 , further comprising:
a third contact within the second current electrode region, wherein sidewalls of the third contact are completely surrounded by the second current electrode region, and the third contact is electrically coupled to the second current electrode region.
6. A semiconductor device comprising:
a gate structure on a substrate; and
a first contact formed in an opening in the gate structure that extends from a top of the gate structure to the substrate, wherein sidewalls of the first contact are completely surrounded by the gate structure, and wherein the first contact is electrically coupled to the gate structure.
7. The semiconductor device of claim 6 , wherein the substrate is an insulator.
8. The semiconductor device of claim 6 , wherein the first contact has a cross-sectional shape selected from a group consisting of a rectangular cross-sectional shape, and a tapered cross-sectional shape having a first width at a top of the first contact and a second width at a bottom of the first contact.
9. The semiconductor device of claim 6 , further comprising:
a first current electrode region;
a second current electrode region; and
a channel region between the first current electrode region and the second current electrode region, wherein the channel region is located in a fin structure, wherein a carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region, and the gate structure overlies the fin structure.