Method for sampling data and apparatus therefor
View Patent ↗A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.
1. A semiconductor device for sampling data in a serial data stream in an electronic device, comprising:
sampling logic, comprising:
input sample path selection logic arranged to enable at least one input sample path;
sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and
transition detection logic arranged to detect transitions within the received input data signal;
wherein the input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values to enable at least one further input sample path comprising a phase having a larger window between logic values, wherein, if it is determined that the phase of the at least one input sample path is optimally valid over a plurality of consecutive samples, the input sample path selection logic is arranged to disable all input sample paths apart from the optimally valid input sample path, wherein the input sample path selection logic is arranged to enable a subset of input sample paths, wherein the subset of input sample paths comprises a sampling input sample path, and at least two comparison input sample paths, one comparison input sample path comprising a clock phase ahead of the clock phase for the sampling input sample path, and one comparison input sample path comprising a clock phase behind the clock phase for the sampling input sample path, wherein the input sample path selection logic is arranged to determine that a phase of the input sample paths is not the phase having a largest window between logic values if a transition within the received input data signal is detected between a sampling point for the sampling input sample path and a sampling point for one of the comparison input sample paths.
2. The semiconductor device of claim 1 , wherein the subset of input sample paths comprise clock signals of nominally equi-spaced phase samples.
3. The semiconductor device of claim 1 , wherein the input sample path selection logic is arranged to enable a subset of eight input sample paths comprising clock signals of nominally 45° separated phases.
4. The semiconductor device of claim 1 , wherein the transition detection logic comprises a plurality of logic gates arranged to perform an XOR comparison of input data samples to detect a transition between consecutive sample points within the input data signal.
5. The semiconductor device of claim 1 , wherein the subset of input sample paths comprises a transition detecting input sample path, and input sample paths a number of phase samples either side of the transition detecting input sample path.
6. The semiconductor device of claim 5 , wherein the input sample path selection logic is arranged to determine that a phase of the input sample paths is not the phase having a largest window between logic values if the transition within the received input data signal is not detected within the transition detecting input sample path sample.
7. The semiconductor device of claim 6 , wherein the input sample path selection logic is arranged to enable a subset of input sample paths, if it is determined that the phase of the input sample path is not the phase having the largest window between logic values.
8. The semiconductor device of claim 5 , wherein the subset of input sample paths further comprises a sampling input sample path for sampling the received input data signal to provide a sampled data output signal, the sampling input sample path comprising a clock phase approximately 180° out of phase with the clock phase of the transition detecting input sample path.
9. The semiconductor device of claim 1 , wherein the subset of input sample paths initially comprises all available input sample paths.
10. The semiconductor device of claim 1 , wherein the at least two comparison input sample paths comprise clock phases approximately 90° separated from the sampling input sample path.
11. The semiconductor device claim 1 , wherein if it is determined that a phase of the input sample paths is not the phase having a largest window between logic values, the input sample path selection logic is arranged to enable a subset of input sample paths such that:
if the transition within the received input data signal is detected between the sampling point for the sampling input sample path and the sampling point for the comparison input sample path comprising a clock phase ahead of that of the sampling input sample path, the phase of the sampling input sample path is decremented by one phase sample.
12. The semiconductor device of claim 1 , wherein if it is determined that a phase of the input sample paths is not the phase having a largest window between logic values, enabling a subset of input sample paths such that if the transition within the received input data signal is detected between the sampling point for the sampling input sample path and the sampling point for the comparison input sample path comprising a clock phase generally behind that of the sampling input sample path, the phase of the sampling input sample path is incremented by one phase sample.
13. The semiconductor device of claim 1 , wherein the sampling input sample path is used for sampling the received input data signal to provide a sampled data output signal.
14. The semiconductor device of claim 1 , wherein the input data signal is received over a BaseBand Integrated Circuit to Radio Frequency Integrated Circuit interface.
15. A wireless communication device, comprising a semiconductor device according to claim 1 .
16. The semiconductor device of claim 10 , wherein the input sample path selection logic is arranged to determine that a phase of the input sample paths is not the phase having a largest window between logic values if a transition within the received input data signal is detected between a sampling point for the sampling input sample path and a sampling point for one of the comparison input sample paths.
17. The semiconductor device of claim 11 wherein the sampling input sample path is used for sampling the received input data signal to provide a sampled data output signal.
18. A method for sampling data in a serial data stream in an electronic device, comprising:
receiving an input data signal in a serial data stream;
enabling a subset of input sample paths comprising a sampling input sample path, and at least two comparison input sample paths, one comparison input sample path comprising a clock phase ahead of the clock phase for the sampling input sample path, and one comparison input sample path comprising a clock phase behind the clock phase for the sampling input sample path;
sampling the received input data in the serial data stream in accordance with a phase of the sampling input sample path; and
detecting transitions within the received input data signal,
upon detection of a transition within the received input data signal, determining if the phase of the sampling input sample path is a phase having a largest window between logic values, wherein the determining is based on whether the transition within the received input data signal is detected between a sampling point for the sampling input sample path and a comparison sampling point for one of the comparison input sample paths; and
if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, enabling at least one further input sample path comprising a phase having a larger window between logic values.
19. A method for sampling data in a serial data stream in an electronic device, comprising:
receiving an input data signal in a serial data stream;
initially enabling a plurality of input clock paths;
sampling the received input data in the serial data stream in accordance with respective phases of the plurality of input clock paths;
detecting a transition within the received input data signal in response to the sampling,
determining a sampling input clock path in response to the detecting;
further sampling the received input data in the serial data stream in accordance with a phase of the sampling input sample path;
upon the detection of the transition within the received input data signal, determining if the phase of the sampling input path is a phase having a largest window between logic values based on detecting whether the transition within the received input data signal is between a sampling point for the sampling input sample path and a comparison sampling point for one of the comparison input sample paths;
in response to the determining, enabling a subset of the input sample paths comprising a sampling input sample path, and at least two comparison input sample paths, one comparison input sample path comprising a clock phase ahead of the clock phase for the sampling input sample path, and one comparison input sample path comprising a clock phase behind the clock phase for the sampling input sample path; and
in response to the determining, disabling remaining input sample paths of the input sample paths not included in the subset, wherein the disabling reduces power consumption of the electronic device.