CMOS device structures
View Patent ↗Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).
1. A complementary metal-oxide semiconductor (CMOS) device structure, comprising:
a first MOS transistor having first source and drain regions of a first conductivity type located in a first semiconductor region of a second, opposite conductivity type;
a second MOS transistor having second source and drain regions of the second conductivity type located in a second semiconductor region of the first conductivity type;
a first further semiconductor region of the first conductivity type proximate the first semiconductor region and located between the first MOS transistor and the second MOS transistor; and
a second further semiconductor region of the second conductivity type proximate the second semiconductor region and located between the first MOS transistor and the second MOS transistor, and wherein the first and second further regions have an ohmic connection therebetween.
2. The device structure of claim 1 , wherein the ohmic connection is electrically floating with respect to reference potential terminals adapted to be coupled to the first and second source-drain regions of the CMOS device structure.
3. The device structure of claim 1 , wherein the first further semiconductor region is formed at the same time as the second semiconductor region and the second further semiconductor region is formed at the same time as the first semiconductor region.
4. The device structure of claim 1 , wherein the first further semiconductor region has a first width and the second further semiconductor region has a second width equal to or larger than the first width.
5. The device structure of claim 4 , wherein the second width is in a range of 2 to 5 times greater than the first width.
6. The device structure of claim 1 , wherein the second semiconductor region has a second depth and the first further semiconductor region has a third depth that is substantially equal to the second depth.
7. The device structure of claim 1 , wherein the first and second further semiconductor regions have substantially rectangular plan view shapes.
8. The device structure of claim 7 , further comprising a still further region of the second conductivity type located laterally outboard of the second semiconductor region of the second transistor and ohmically coupled to one or both of the first and second further semiconductor regions.
9. The device structure of claim 1 , wherein the first further semiconductor region has a ring shape, substantially surrounding the first MOS transistor.
10. The device structure of claim 1 , wherein the first further semiconductor region comprises two BAR portions, a first BAR portion located between the first MOS transistor and the second MOS transistor and a second bar portion spaced apart from and substantially parallel to the first BAR portion and adjacent the first CMOS transistor in a location remote from the second CMOS transistor.
11. The device structure of claim 1 , wherein the first MOS transistor, the first further semiconductor region, the second further semiconductor region, and the second MOS transistor are laterally arranged in that order.
12. An electronic device having first and second field effect transistors of opposite conductivity types, comprising:
a first region of a first conductivity type having therein source-drain regions of a second conductivity type opposite the first conductivity type, thereby forming the first field effect transistor;
a second region of the second conductivity type having therein source-drain regions of the first conductivity type, thereby forming the second field effect transistor; and
third and fourth ohmically coupled regions of, respectively, second and first conductivity types, located between the first region and the second region.
13. The electronic device of claim 12 , wherein the third region is proximate the first region.
14. The electronic device of claim 12 , wherein the electronic device is adapted to receive a reference potential at a first terminal and a power supply potential at a second terminal, and neither of the third and fourth regions is ohmically coupled to the first or second terminals.
15. The electronic device of claim 12 , wherein the third region has a third width and the fourth region has a fourth width, and wherein the fourth width divided by the third width forms a ratio R≧1.
16. The electronic device of claim 15 , wherein 2≦R≦5.
17. The electronic device of claim 12 , wherein the first and second field effect transistors are coupled so as to form an inverter.
18. A complementary metal-oxide semiconductor (CMOS) device structure, comprising:
a substrate;
a first well region of a first conductivity type in the substrate;
a second well region of a second, opposite, conductivity type in the substrate, wherein the second well region is laterally separated from the first well region by a first distance;
a first further region of the first conductivity type in the substrate between the first and second well regions, proximate the second well region;
a second further region of the second conductivity type in the substrate between the first and second well regions, proximate the first well region;
first source-drain regions of the first conductivity type in the second well region;
a first contact region of the first conductivity type in the first well region;
a second contact region of the first conductivity type in the first further region;
second source-drain regions of the second conductivity type in the first well region;
a third contact region of the second conductivity type in the second well region; and
a fourth contact region of the second conductivity type in the second further region, wherein the second and fourth contact regions are ohmically coupled.
19. The device structure of claim 18 , wherein the first further region has a first width and the second further region has a second width and the first width equals or exceeds the second width.
20. The device structure of claim 18 , further comprising:
a still further contact region of the first conductivity type in the substrate laterally outside the second well region and ohmically coupling the still further contact region to one or both of the first and second further regions.