IP Library Granted Patent US 8,639,468
Granted Patent B2
US 8,639,468 · App. 13/056,322 · Granted Jan 28, 2014

Die temperature estimator

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Quick Facts
Patent No.
US 8,639,468
App. No.
13/056,322
Granted
Jan 28, 2014
Kind
B2
Abstract

A temperature estimation circuit for estimating a temperature of an integrated circuit die comprises a temperature increase estimation circuit, having inputs operable to receive notification signals, each corresponding to a command signal passed to an integrated circuit, and an output providing a sum of temperature increase values, each corresponding to a temperature increase of the integrated circuit due to one of the command signals. The circuit further comprises a temperature decrease estimation circuit, having an input operable to receive a calculated die temperature value, and an output providing a temperature decrease value depending on a mathematical model of temperature decrease when no command signal is applied. The circuit further comprises a temperature calculation circuit, having a first input connected to the output of the temperature increase estimation circuit, a second input connected to the output of the temperature decrease estimation circuit, and an output providing the calculated die temperature value.

Claims (33)

1. A temperature estimation circuit for estimating a temperature of a die of an integrated circuit, comprising:

a temperature increase estimation circuit, having one or more inputs operable to receive one or more notification signals, each notification signal corresponding to a command signal passed to said integrated circuit, and

having an output operable to provide a sum of one or more temperature increase values, each temperature increase value corresponding to a temperature increase of said integrated circuit due to one of said command signals;

a temperature decrease estimation circuit, comprising:

an input operable to receive a calculated die temperature value, and

an output operable to provide a temperature decrease value depending on a mathematical model of temperature decrease, when no command signal is applied to said integrated circuit; and

a temperature calculation circuit, having

a first input connected to said output of said temperature increase estimation circuit,

having a second input connected to said output of said temperature decrease estimation circuit, and

having an output operable to provide said calculated die temperature value.

2. The temperature estimation circuit as claimed in claim 1 , wherein said temperature calculation circuit comprises a calculator for calculating said die temperature value from at least one previous die temperature value increased by said sum of one or more temperature increase values and decreased by said temperature decrease value.

3. The temperature estimation circuit as claimed in claim 2 , wherein said temperature decrease estimation circuit is arranged to provide said temperature decrease value as a scaled difference of said calculated die temperature value and an estimated die temperature value when no command signal is applied to said integrated circuit.

4. The temperature estimation circuit as claimed in claim 2 , wherein said temperature increase estimation circuit comprises one or more switches, each switch having an input for one of said temperature increase values, each temperature increase value corresponding to a temperature increase of said integrated circuit due to one of said command signals.

5. The temperature estimation circuit as claimed in claim 2 , wherein said temperature increase estimation circuit comprises one or more inputs operable to receive said one or more temperature increase values.

6. The temperature estimation circuit as claimed in claim 2 , wherein said integrated circuit is a memory device.

7. The temperature estimation circuit as claimed in claim 1 , wherein said temperature decrease estimation circuit is arranged to provide said temperature decrease value as a scaled difference of said calculated die temperature value and an estimated die temperature value when no command signal is applied to said integrated circuit.

8. The temperature estimation circuit as claimed in claim 7 , wherein said difference is scaled using a scaler having a programmable scaling factor input.

9. The temperature estimation circuit as claimed in claim 8 , wherein said temperature decrease estimation circuit comprises an input for applying said estimated die temperature value when no command signal is applied to said integrated circuit.

10. The temperature estimation circuit as claimed in claim 8 , wherein said temperature increase estimation circuit comprises one or more switches, each switch having an input for one of said temperature increase values, each temperature increase value corresponding to a temperature increase of said integrated circuit due to one of said command signals.

11. The temperature estimation circuit as claimed in claim 7 , wherein said temperature decrease estimation circuit comprises an input for applying said estimated die temperature value when no command signal is applied to said integrated circuit.

12. The temperature estimation circuit as claimed in claim 7 , wherein said temperature increase estimation circuit comprises one or more switches, each switch having an input for one of said temperature increase values, each temperature increase value corresponding to a temperature increase of said integrated circuit due to one of said command signals.

13. The temperature estimation circuit as claimed in claim 7 , wherein said temperature increase estimation circuit comprises one or more inputs operable to receive said one or more temperature increase values.

14. The temperature estimation circuit as claimed in claim 7 , wherein said integrated circuit is a memory device.

15. The temperature estimation circuit as claimed in claim 1 , wherein said temperature increase estimation circuit comprises one or more switches, each switch having an input for one of said temperature increase values, each temperature increase value corresponding to a temperature increase of said integrated circuit due to one of said command signals.

16. The temperature estimation circuit as claimed in claim 1 , wherein said temperature increase estimation circuit comprises one or more inputs operable to receive said one or more temperature increase values.

17. The temperature estimation circuit as claimed in claim 1 , wherein said integrated circuit is a memory device.

18. A method for estimating a temperature of a die of an integrated circuit, comprising:

receiving one or more notification signals, at a temperature increase estimation device, from a data processing device, each notification signal corresponding to a command signal passed to said integrated circuit;

providing to a temperature calculation device, from the temperature increase estimation device, a sum of one or more temperature increase values, each temperature increase value corresponding to a temperature increase of said integrated circuit due to one of said command signals;

providing to the temperature calculation device, from a temperature decrease estimation device, a temperature decrease value depending on a mathematical model of temperature decrease, when no command signal is applied to said integrated circuit; and

providing to the data processing device, from the temperature calculation device, a calculated die temperature value depending on said sum of one or more temperature increase values, said temperature decrease value, and at least one previous die temperature value.

19. A data processing system, comprising the integrated circuit and the temperature estimation circuit as claimed in claim 1 and a data processing device operable to send one or more command signals to said integrated circuit and one or more corresponding notification signals to said temperature estimation circuit.

20. The data processing system as claimed in claim 19 , wherein said data processing device adjusts a number of command signals per unit time sent to said integrated circuit depending on said calculated die temperature value.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2011
From: CLOETENS, HENRI
To: FREESCALE SEMICONDUCTOR INC.
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