LDMOS with enhanced safe operating area (SOA) and method therefor
View Patent ↗A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.
1. A laterally double diffused metal oxide semiconductor device comprising:
a first well region having a first conductivity type;
a first doped region having a second conductivity type, wherein
the first doped region is adjacent to, aligned with, and below the first well region, and
the second conductivity type is different in type than the first conductivity type;
a first doped buried semiconductor region having the first conductivity type,
wherein:
the first doped buried semiconductor region is under the first well region but is not in physical contact with the first well region,
the first doped buried semiconductor region is under the first doped region and in contact with the first doped region,
the first doped region extends below a top surface of the first doped buried semiconductor region and is adjacent to at least a portion of at least one side of the first doped buried semiconductor region, and
the first doped buried semiconductor region is capable of redistributing carriers in the first well region;
an epitaxial layer having the second conductivity type, wherein
the epitaxial layer is adjacent to at least a portion of the first doped region,
the epitaxial layer is adjacent to a bottom surface of the first doped buried semiconductor region and a portion of the at least one side of the first doped buried semiconductor region that is not adjacent to the first doped region, and
the first doped region is doped at a concentration greater than that of the epitaxial layer;
a buried layer under the first doped buried semiconductor region, wherein:
the buried layer has the first conductivity type,
the buried layer is doped at a concentration greater than that of the first well region and greater than that of the first doped buried semiconductor region, and
the buried layer is electrically tied to the first well region.
2. The device of claim 1 , further comprising a drain contact region within the first well region, wherein:
the drain contact region has the first conductivity type, is highly doped at a concentration greater than that of the first well region.
3. The device of claim 2 , further comprising a second well region laterally adjacent the first well region, wherein the second well region has the second conductivity type.
4. The device of claim 3 , further comprising:
a first source region within the second well region, wherein the first source region has the second conductivity and is doped at a concentration greater than that of the second well region; and
a second source region within the second well region, wherein:
the second source region has the first conductivity type and is doped at a concentration greater than that of the second well region; and
the second source region is electrically shorted to the first source region.
5. The device of claim 4 , further comprising:
a gate insulating layer over a portion of the first well region, a portion of the second well region, and a portion of the epitaxial layer; and
a gate electrode over the gate insulating layer, the portion of the first well region, the portion of the second well region, and the portion of the epitaxial layer.
6. The device of claim 5 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
7. The device of claim 2 , wherein the first doped buried semiconductor region is under the drain contact region.
8. The device of claim 7 , wherein the first doped buried semiconductor region is also under a portion of the gate electrode.
9. The device of claim 7 , further comprising a second doped buried semiconductor region having the first conductivity type, wherein:
the second doped buried semiconductor region is under the first well region but is not in physical contact with the first well region; and
the second doped buried semiconductor region is capable of redistributing carriers in the first well region.
10. The device of claim 9 , wherein the first doped buried semiconductor region is above the second doped buried semiconductor region.
11. The device or claim 9 , wherein the first doped buried semiconductor region is laterally adjacent the second doped buried semiconductor region.