Granted Patent B2

US 8,487,398 · App. 12/835,900 · Granted Jul 16, 2013

Abstract

Claims (39)

1. A semiconductor device comprising:

an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device;

a capacitor dielectric over the isolated p-type well;

a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device;

a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode, and functions as a contact while being p-type;

a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, and functions as a contact while being p-type, wherein a portion of the isolated p-type well between the first p-type contact region and the second p-type contact region is under the p-type polysilicon electrode and the capacitor dielectric;

an n-type isolation region surrounding the isolated p-type well on sides and a bottom of the isolated p-type well;

a p-type semiconductor substrate, wherein the isolated p-type well is over the semiconductor substrate, and a horizontal portion of the n-type isolation region between the isolated p-type well and the p-type semiconductor substrate to isolate the isolated P-type well from the P-type semiconductor substrate;

a semiconductor layer over the p-type substrate layer, wherein the isolated p-type well is in the semiconductor layer, and wherein a vertical portion of the n-type isolation region is between the isolated p-type well and the semiconductor layer; and

a trench isolation region in the semiconductor layer comprised of an insulating material having an opening therethrough filled with conductive material, wherein the trench isolation region is over and in physical contact with the vertical portion of the n-type isolation region and the conductive material is in physical and electrical contact with a portion of the vertical portion of the n-type isolation region, and wherein the first p-type contact region extends laterally from the first sidewall of the p-type polysilicon electrode to the trench isolation region and the second p-type contact region extends laterally from the second sidewall of the p-type polysilicon electrode to the trench isolation region.

2. The semiconductor device of claim 1 , wherein the trench isolation region and the n-type isolation region, in combination, fully isolates the isolated p-type well from the semiconductor layer and the p-type semiconductor substrate.

3. The semiconductor device of claim 1 , wherein each of the first p-type contact region, the second p-type contact region, and the p-type polysilicon electrode is more heavily doped as compared to the isolated p-type well.

4. The semiconductor device of claim 1 , wherein a thickness of the capacitor dielectric is not greater than 30 Angstroms.

5. The semiconductor device of claim 1 , further comprising:

a fringe capacitor over the p-type polysilicon electrode, wherein a first electrode of the fringe capacitor is electrically coupled to each of the first p-type contact region and the second p-type contact region, and a second electrode of the fringe capacitor is electrically coupled to the p-type polysilicon electrode.

6. The semiconductor device of claim 1 , further comprising:

a fringe capacitor over the p-type polysilicon electrode and the isolated P well and electrically coupled in parallel with the capacitor device.

7. The semiconductor device of claim 1 , further comprising:

a sidewall spacer adjacent the first and second sidewalls of the p-type polysilicon electrode and over a portion of the first p-type contact region and over a portion of the second p-type contact region.

8. A semiconductor device comprising

a p-type semiconductor substrate;

a buried n-type layer over the p-type semiconductor substrate;

a semiconductor layer formed over the p-type semiconductor substrate;

an isolated p-type well in the semiconductor layer, wherein the isolated p-type well is over and in contact with the buried n-type layer and is a first electrode of a capacitor device, wherein the n-type layer functions to isolate the isolated p-type well from the p-type semiconductor substrate on a bottom side of the isolated p-type well;

a capacitor dielectric over the isolated p-type well;

a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device;

a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode, and functions as a contact while being p-type;

a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, and functions as a contact while being p-type, wherein a portion of the isolated p-type well between the first p-type contact region and the second p-type contact region is under and in contact with the capacitor dielectric;

a vertical n-type isolation region in the semiconductor layer, wherein the vertical n-type isolation region is over and in contact with the buried n-type layer and surrounds the isolated p-type well; and

a trench isolation region in the semiconductor layer comprised of an insulating material having an opening therethrough filled with conductive material, wherein the trench isolation region is over and in physical contact with the vertical n-type isolation region and the conductive material is in physical and electrical contact with a portion of the vertical portion n-type isolation region.

9. The semiconductor device of claim 8 , wherein:

p-type polysilicon electrode to the trench isolation region and the second p-type contact region extends laterally from the second sidewall of the p-type polysilicon electrode to the trench isolation region.

10. The semiconductor device of claim 9 , wherein the trench isolation region and the n-type isolation region, in combination, isolate sides of the isolated p-type well from the semiconductor layer.

11. The semiconductor device of claim 9 , further comprising:

a sidewall spacer adjacent the first and second sidewalls of the p-type polysilicon electrode, wherein the sidewall spacer is over a portion of the first p-type contact region and over a portion of the second p-type contact region.

12. The semiconductor device of claim 11 , wherein each of the first p-type contact region, the second p-type contact region, and the p-type polysilicon electrode is more heavily doped as compared to the isolated p-type well.

13. The semiconductor device of claim 11 , wherein a thickness of the capacitor dielectric is not greater than 30 Angstroms.

14. The semiconductor device of claim 8 , further comprising:

a fringe capacitor over the p-type polysilicon electrode, wherein a first electrode of the fringe capacitor is electrically coupled to each of the first p-type contact region and the second p-type contact region, and a second electrode of the fringe capacitor is electrically coupled to the p-type polysilicon electrode.

Assignments (22)