Multistage voltage regulator circuit
View Patent ↗Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.
1. A multistage voltage regulator circuit comprising:
a first stage, the first stage comprising:
a first circuit module including a first plurality of memory cells of a first memory array, the first circuit module including a first voltage supply terminal;
a first regulated node, the first regulated node is connected to the first voltage supply terminal of the first circuit module to supply a first supply voltage to the first voltage supply terminal, wherein current flowing through the first voltage supply terminal supplies power to the first plurality of memory cells; and
a first bias transistor including a first current terminal coupled to a first power supply terminal and a second current terminal coupled to the first regulated node;
a second stage, the second stage comprising:
a second circuit module including a second plurality of memory cells of a second memory array, the second circuit module including a second voltage supply terminal;
a second regulated node, the second regulated node is connected to the second voltage supply terminal of the second circuit module to supply a second supply voltage to the second voltage supply terminal, wherein current flowing through the second voltage supply terminal of the second circuit module supplies power to the second plurality of memory cells; and
a second bias transistor including a first current terminal coupled to the first power supply terminal and a second current terminal coupled to the second regulated node;
a bias stage, the bias stage comprising:
a third node, and
a third bias transistor including a first current terminal coupled to the first power supply terminal and a second current terminal coupled to the third node; and
a control loop for regulating the first supply voltage of the first regulated node and the second supply voltage of the second regulated node, wherein the control loop includes the first bias transistor, the second bias transistor, the third bias transistor, the first regulated node, the second regulated node, and the third node, wherein the control loop includes a coupling of a control terminal of the first bias transistor to the second regulated node, and wherein the control loop further includes a coupling of the first regulated node to a control terminal of the third bias transistor.
2. The multistage voltage regulator circuit of claim 1 wherein
the bias stage including a load transistor, wherein a first current terminal of the load transistor is coupled to the third node.
3. The multistage voltage regulator circuit of claim 1 wherein the control loop includes a coupling of the third node to a control terminal of the second bias transistor.
4. The multistage voltage regulator circuit of claim 1 wherein:
the first voltage supply terminal of the first circuit module and the second voltage supply terminal of the second circuit module are characterized as low voltage supply terminals; and
the first power supply terminal is characterized as a low voltage power supply terminal.
5. The multistage voltage regulator circuit of claim 1 wherein:
the first voltage supply terminal of the first circuit module and the second voltage supply terminal of the second circuit module are characterized as high voltage supply terminals; and
the first power supply terminal is characterized as a high voltage power supply terminal.
6. The multistage voltage regulator circuit of claim 1 wherein;
the first stage includes a first activation transistor including a first current terminal coupled to the first power supply terminal and a second current terminal coupled to the first regulated node, and a control terminal coupled to receive a first signal;
the second stage includes a second activation transistor including a first current terminal coupled to the first power supply terminal, a second current terminal coupled to the second regulated node, and a control terminal coupled to receive the first signal;
wherein when the first signal is in a first state, the first activation transistor is conductive to bias the first regulated node at a voltage of the first power supply terminal and the second activation transistor is conductive to bias the second regulated node at the voltage of the first power supply terminal; and
wherein when the first signal is in a second state, the first activation transistor and the second activation transistor are non conductive wherein the control loop controls the first supply voltage of the first regulated node and the second supply voltage of the second regulated node.
7. The multistage voltage regulator circuit of claim 1 further comprising:
a frequency counter including an input coupled to one of the first regulated node or the second regulated node and an output to provide an indication of a frequency of oscillation of a voltage of the first regulated node or the second regulated node that is connected to the input.
8. The circuit of claim 1 wherein the control loop is designed to be stable during operation.
9. The multistage voltage regulator circuit of claim 2 wherein:
the first circuit module includes a third voltage supply terminal, the third voltage supply terminal of the first circuit module is coupled to a second power supply terminal;
the second circuit module includes a fourth voltage supply terminal, the fourth voltage supply terminal of the second circuit module is coupled to the second power supply terminal; and
a second current terminal of the load transistor is coupled to the second power supply terminal.
10. The multistage voltage regulator circuit of claim 9 wherein
the third voltage supply terminal of the first circuit module and the fourth voltage supply terminal of the second circuit module are characterized as high voltage supply terminals; and
the second power supply terminal is characterized as a high voltage power supply terminal.
11. The multistage voltage regulator circuit of claim 9 wherein
the third voltage supply terminal of the first circuit module and the fourth voltage supply terminal of the second circuit module are characterized as low voltage supply terminals; and
the second power supply terminal is characterized as a low voltage power supply terminal.
12. A circuit comprising:
a first stage, the first stage comprising:
a first circuit module including a first plurality of memory cells, the first circuit module including a first voltage supply terminal;
a first regulated node, the first regulated node is connected to the first voltage supply terminal to supply a first supply voltage to the first voltage supply terminal, wherein current flowing through the first voltage supply terminal supplies power to the first plurality of memory cells; and
a first bias transistor including a first current terminal coupled to a first power supply terminal and a second current terminal connected to the first regulated node;
a second stage, the second stage comprising:
a second circuit module including a second plurality of memory cells, the second circuit module including a second voltage supply terminal;
a second regulated node, the second regulated node is connected to the second voltage supply terminal of the second circuit module to supply a second supply voltage to the second voltage supply terminal, wherein current flowing through the second voltage supply terminal of the second circuit module supplies power to the second plurality of memory cells; and
a second bias transistor including a first current terminal coupled to the first power supply terminal and a second current terminal connected to the second regulated node; and
a third stage, the third stage comprising:
a third regulated node; and
a third bias transistor including a first current terminal coupled to the first power supply terminal and a second current terminal connected to the third regulated node;
wherein the second regulated node is connected to a control terminal of the first bias transistor; and
wherein the first regulated node is connected to a control terminal of the third bias transistor.
13. The circuit of claim 12 wherein the third stage includes a third circuit module including a third voltage supply terminal connected to the third regulated node.
14. The circuit of claim 12 further comprising:
a frequency counter including an input coupled to one of the first regulated node, the second regulated node, or the third regulated node, and an output to provide an indication of a frequency of oscillation of a voltage of the first regulated node, the second regulated node, or the third regulated node that is coupled to the input of the frequency counter.
15. The circuit of claim 12 wherein the third stage includes a load transistor including a first current terminal connected to the third regulated node and a control terminal connected to the third regulated node.
16. The circuit of claim 12 wherein:
the first stage includes a first activation transistor including a first current terminal coupled to the first power supply terminal and a second current terminal connected to the first regulated node, and a control terminal coupled to receive a first signal;
the second stage includes a second activation transistor including a first current terminal coupled to the first power supply terminal, a second current terminal connected to the second regulated node, and a control terminal coupled to receive the first signal;
wherein when the first signal is in a first state, the first activation transistor is conductive to bias the first regulated node at a voltage of the first power supply terminal and the second activation transistor is conductive to bias the second regulated node at the voltage of the first power supply terminal;
wherein when the first signal is in a second state, the first activation transistor and the second activation transistor are non conductive, wherein the first supply voltage of the first regulated node is regulated by the second supply voltage of the second regulated node and a voltage of the third regulated node is regulated by the first supply voltage of the first regulated node.
17. The circuit of claim 12 where the first circuit module and the second circuit module each include a memory array.
18. The circuit of claim 12 wherein the third stage includes a third activation transistor including a first current terminal coupled to the first power supply terminal, a second current terminal connected to the third regulated node, and a control terminal coupled to receive the first signal.
19. A circuit comprising:
a plurality of N+1 stages connected in a series in a loop, wherein N is an even integer of two or greater, wherein each stage of the plurality of stages comprises:
a circuit module including a plurality of memory cells;
a regulated node connected to a voltage supply terminal of the circuit module of the each stage to supply a supply voltage to the voltage supply terminal, wherein current flowing through the voltage supply terminal supplies power to the plurality of memory cells of each stage;
a bias transistor including a first current terminal connected to the regulated node of the each stage and a second current terminal coupled to a power supply terminal;
wherein for each stage of the plurality of stages, the regulated node of the each stage of the plurality of stages is connected to a control terminal of a bias transistor of a previous stage of the plurality of N+1 stages, wherein the previous stage is adjacent to the each stage in the series in a first direction of the loop, and a control terminal of the bias transistor of the each stage is connected to a regulated node of a subsequent stage of the plurality of N+1 stages, wherein the subsequent stage is adjacent to the each stage in the series in a second direction of the loop, wherein the second direction is opposite the first direction.
20. The circuit of claim 19 further comprising:
a frequency counter including an input coupled to a regulated node of a stage of the plurality of stages and an output to provide an indication of a frequency of oscillation of a voltage of the regulated node that the input is coupled to.
21. The circuit of claim 19 wherein the circuit module of each stage of the plurality of stages includes a memory array.