Transistor having gate dielectric protection and structure
View Patent ↗A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.
1. A transistor comprising:
a semiconductor substrate;
a gate stack overlying the semiconductor substrate and comprising a gate dielectric and an overlying gate electrode;
a relatively thin sidewall spacer dielectric along sidewalls of the gate dielectric and the gate electrode, wherein
a layer forming the relatively thin sidewall spacer dielectric has a thickness of about a tenth of the width of the gate electrode;
a barrier layer adjacent each of an outer edge of the opposing vertical sides of a channel, the barrier layer comprising a dopant blocking species to impede migration of a dopant species, wherein
a vertical portion of the barrier layer is vertically aligned to the relatively thin sidewall spacer dielectric;
the channel underlying the gate electrode and the gate dielectric, wherein the channel comprises opposing vertical sides adjacent the barrier layer;
a source and a drain adjacent the opposing vertical sides of the channel and separated from the channel by the barrier layer, each of the source and the drain comprising the dopant species;
a second sidewall spacer adjacent to the relatively thin sidewall spacer dielectric and overlying a portion of the source and drain, wherein the second sidewall spacer is relatively thick compared to the relatively thin sidewall spacer; and
a deep source region and a deep drain region underlying a portion of the source and drain respectively, wherein
a channel-side boundary of the deep source region and the deep drain region are vertically aligned to the second sidewall spacer, and
each of the deep source region and the deep drain region comprise the dopant species.
2. The transistor of claim 1 wherein the barrier layer comprises a predetermined concentration of nitrogen.
3. The transistor of claim 1 wherein the barrier layer comprises a predetermined concentration of carbon.
4. The transistor of claim 1 wherein the dopant species comprises boron.
5. The transistor of claim 4 wherein the source and drain are grown using an epitaxy process and in situ doped with the dopant species.
6. The transistor of claim 1 wherein the relatively thin sidewall spacer comprises nitride.
7. The transistor of claim 1 wherein the second sidewall spacer comprises nitride with an oxide liner.
8. The transistor of claim 1 further comprising:
a gate electrical contact overlying the gate stack;
a source electrical contact overlying the source; and
a drain electrical contact overlying the drain.
9. The transistor of claim 1 wherein the source and drain are formed using a stressor material, wherein the stressor material provides stress to the channel of the transistor.
10. A transistor comprising:
a semiconductor substrate;
a gate stack overlying the semiconductor substrate and comprising a gate dielectric and an overlying gate electrode;
a relatively thin sidewall spacer dielectric along sidewalls of the gate dielectric and the gate electrode, wherein
a layer forming the relatively thin sidewall spacer dielectric has a thickness of about a tenth of the width of the gate electrode;
a channel underlying the gate electrode and the gate dielectric, wherein the channel comprises opposing vertical sides;
a barrier layer adjacent each of an outer edge of the opposing vertical sides of the channel, the barrier layer comprising one of a group of nitrogen and carbon to form a dopant species diffusion barrier, wherein
a vertical portion of the barrier layer is vertically aligned to the relatively thin sidewall spacer dielectric;
a horizontal portion of the barrier layer overlying a source recess and a drain recess in the substrate; and
a semiconductor source overlying the horizontal portion of the barrier layer over the source recess and a semiconductor drain overlying the horizontal portion of the barrier layer over the drain recess, wherein
the semiconductor source and drain are in situ doped with the dopant species, and
the semiconductor source and drain are adjacent the opposing vertical sides of the channel and separated from the channel by the barrier layer wherein the transistor further comprises a second sidewall spacer adjacent the relatively thin sidewall spacer, wherein the second sidewall spacer is relatively thick compared to the relatively thin sidewall spacer.
11. The transistor of claim 10 wherein the dopant species is boron.
12. The transistor of claim 10 further comprising:
a deep source region formed in the semiconductor substrate beneath the semiconductor source and the corresponding horizontal portion of the barrier layer; and
a deep drain region formed in the semiconductor substrate beneath the semiconductor drain and the corresponding horizontal portion of the barrier layer.
13. The transistor of claim 12 wherein the deep source region and the deep drain region are formed using the second sidewall spacer as a mask.
14. The transistor of claim 10 wherein the semiconductor source and the semiconductor drain comprise a semiconductor stressor material.
15. The transistor of claim 14 wherein a concentration of the dopant species diffusion barrier of the barrier layer is less than 1e19 atoms per cubic centimeter of the one of the group of nitrogen and carbon.