Data processing system having selective redundancy and method therefor
View Patent ↗A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction.
1. A method comprising:
decoding an instruction a first time to obtain a first decoded instruction;
decoding the instruction a second time to obtain a second decoded instruction;
comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction;
when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction;
when the at least the portion of the first decoded instruction does not match the at least the portion of the second instruction, not executing the instruction;
providing a counter corresponding to each instruction class of a plurality of instruction classes; and
when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, the method further comprises:
providing the instruction to an execution unit of a data processing system;
updating the counter corresponding to the instruction class of the instruction by a predetermined amount;
determining that a stored value of the updated counter matches a predetermined value; and
performing redundant execution on the instruction in response to determining that the stored value of the updated counter matches the predetermined value.
2. The method of claim 1 , wherein when the first decoded instruction does not match the second decoded instruction, generating an exception.
3. The method of claim 1 , wherein the instruction class comprises a function selected from a group consisting of load, store, multiply, divide, branch, add, shift, and jump.
4. The method of claim 1 , further comprising:
determining that the instruction encountered an error during execution; and
updating a counter corresponding to an instruction class of the executed instruction by a second predetermined value.
5. The method of claim 1 , wherein performing redundant execution on the instruction further comprises executing the instruction in an execution unit at least two consecutive times and comparing results of the execution.
6. The method of claim 1 , further comprising storing at least a portion of the first decoded instruction.
7. In a data processing system having an execution unit, a method comprising:
providing a counter corresponding to each instruction class of a plurality of instruction classes;
providing an instruction to an execution unit of a data processing system;
updating the counter corresponding to the instruction class of the instruction by an amount;
determining that a stored value of the updated counter is above a predetermined value; and
performing redundant execution on the instruction in response to determining that the stored value of the updated counter is above the predetermined value.
8. The method of claim 7 , wherein the instruction class comprises a function selected from a group consisting of load, store, multiply, divide, branch, add, shift, and jump.
9. The method of claim 7 , further comprising:
determining that the instruction encountered an error during execution; and
updating a counter corresponding to an instruction class of the executed instruction by a second predetermined value.
10. The method of claim 7 , wherein performing redundant execution on the instruction further comprises executing the instruction in an execution unit at least two consecutive times and comparing results of the execution.
11. A data processing system comprising:
an execution unit for executing instructions;
a plurality of counters, one counter of the plurality of counters corresponding to an instruction class of a plurality of instruction classes;
an instruction decode unit for decoding instructions to be executed; and
a redundant decode control unit coupled to the instruction decode unit, the redundant decode control unit configured to cause an instruction to be decoded twice in the instruction decode unit producing a first decoded instruction and a second decoded instruction, wherein the redundant decode control unit is configured to cause at least a portion of the first decoded instruction to be compared to at least a portion of the second decoded instruction, and when the portion of the first decoded instruction matches the portion of the second decoded instruction, the redundant decode control unit is configured to cause the first decoded instruction to be provided to the execution unit, and further configured to update the counter corresponding to the instruction class of the instruction by a predetermined amount, determining that a stored value of the updated counter matches the predetermined value, and performing redundant execution on the instruction in response to the stored value of the updated counter matching the predetermined value.
12. The data processing system of claim 11 , further comprising a decode storage unit configured to store the first decoded instruction.
13. The data processing system of claim 11 , wherein each of the plurality of instruction classes comprises a function selected from a group consisting of load, store, multiply, divide, branch, add, shift, and jump.
14. The data processing system of claim 11 , wherein the execution unit, instruction decode unit, redundant decode control unit are part of a processor implemented on a single integrated circuit.