IP Library Granted Patent US 8,431,970
Granted Patent B2
US 8,431,970 · App. 12/884,807 · Granted Apr 30, 2013

Integrated circuits with edge-adjacent devices having reactance values

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Quick Facts
Patent No.
US 8,431,970
App. No.
12/884,807
Granted
Apr 30, 2013
Kind
B2
Abstract

An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.

Claims (34)

1. An integrated circuit comprising:

at least one device adjacent an outer edge of the integrated circuit, wherein the at least one device comprises a plurality of capacitors that includes:

a continuous outer metal conductor around the outer edge of the integrated circuit for forming an edge seal for protecting the integrated circuit during die singulation and for functioning as a common first electrode, and

a plurality of second electrodes, the plurality of second electrodes comprising an electrically discontinuous inner metal conductor located between the plurality of pads and the first electrode; and

a functional circuit within the integrated circuit having a first terminal connected to a first portion of the at least one device and having a second terminal connected to a second portion of the at least one device, the at least one device providing a reactance value to the functional circuit for non-test operational use by the functional circuit.

2. The integrated circuit of claim 1 wherein the plurality of capacitors each couple capacitance to the functional circuit during non-testing operation of the integrated circuit.

3. An integrated circuit comprising:

a functional circuit having a first terminal and a second terminal; and

a capacitor adjacent an outer edge of the integrated circuit, the capacitor providing a reactance value to the functional circuit for non-test operational use by the functional circuit, and the capacitor including:

a first metal electrode encircling the outer edge of the integrated circuit and having at least one opening, the first metal electrode connected to the functional circuit at the first terminal, the first metal electrode having an opening therein within a portion that encircles the outer edge of the integrated circuit, the first metal electrode forming a first electrode of the capacitor that is connected to the functional circuit, and

a second metal electrode encircling the outer edge of the integrated circuit between the outer edge and the first metal electrode, the second metal electrode forming an edge seal for protecting the integrated circuit during die singulation, and extending through the opening of the first metal electrode and connecting to the functional circuit to function as a second electrode of the capacitor.

4. The integrated circuit of claim 3 wherein the opening within the first metal electrode is formed only through an underlying portion of the first metal electrode.

5. An integrated circuit comprising:

a plurality of terminals for making electrical connection to the integrated circuit;

at least one device adjacent an outer edge of the integrated circuit, the at least one device comprising at least one metal conductor and a plurality of capacitors, wherein the at least one metal conductor is for forming an edge seal for protecting the integrated circuit during die singulation, and the plurality of capacitors comprises a common first electrode and a plurality of second electrodes, the common first electrode comprising a continuous outer metal conductor around the outer edge of the integrated circuit, and the plurality of second electrodes comprising an electrically discontinuous inner metal conductor located between the plurality of terminals and the first electrode; and

one or more functional circuits within the integrated circuit, wherein the one or more functional circuits are coupled to the at least one device with the at least one metal conductor, and wherein the at least one device provides a reactance value to the one or more functional circuits for non-test operational use.

6. The integrated circuit of claim 5 wherein the at least one device further comprises:

an inductor that couples inductance to the one or more functional circuits during a non-testing operation of the integrated circuit.

7. The integrated circuit of claim 6 wherein the inductor comprises:

a continuous metal conductor having a first end electrically connected to a first terminal of a predetermined one of the one or more functional circuits and a second end electrically connected to a second terminal of the predetermined one of the one or more functional circuits, the inductor looping at least once around the integrated circuit between the outer edge and the plurality of terminals.

8. The integrated circuit of claim 5 , wherein each of the plurality of capacitors couples a capacitance to any of the one or more functional circuits during non-testing operation of the integrated circuit.

9. The integrated circuit of claim 5 wherein the at least one device is formed between an outer edge of the integrated circuit and the plurality of terminals.

10. The integrated circuit of claim 5 , wherein the common first electrode is coupled to a first power supply pad, and one of the plurality of second electrodes is coupled to a second power supply pad.

11. An integrated circuit comprising:

a plurality of terminals for making electrical connection to the integrated circuit;

at least one device adjacent a periphery of the integrated circuit, wherein the at least one device comprises a first metal conductor and a plurality of capacitors, wherein the first metal conductor extends entirely around the integrated circuit to form an edge seal for protecting the integrated circuit during die singulation, and the plurality of capacitors comprises a common first electrode and a plurality of second electrodes, wherein the common first electrode comprises a continuous outer metal conductor around the periphery of the integrated circuit, and the plurality of second electrodes comprises an electrically discontinuous metal conductor located between the plurality of terminals and the first electrode; and

a functional circuit within the integrated circuit coupled to the at least one device by routing between the first metal conductor and the functional circuit, the functional circuit implementing non-test functions within the integrated circuit by using the at least one device.

12. The integrated circuit of claim 11 wherein the at least one device is formed between an outer edge of the integrated circuit and the plurality of terminals.

13. The integrated circuit of claim 11 wherein the at least one device further comprises:

an inductor.

14. The integrated circuit of claim 13 wherein the inductor comprises:

a continuous metal conductor having a first end electrically connected to a first terminal of the functional circuit and a second end electrically connected to a second terminal of the functional circuit, the inductor looping around the periphery of the integrated circuit at least once.

15. The integrated circuit of claim 13 wherein the inductor couples inductance to the one or more functional circuits during a non-testing operation of the integrated circuit.

16. The integrated circuit of claim 11 , wherein the common first electrode is coupled to a first power supply pad, and one of the plurality of second electrodes is coupled to a second power supply pad.

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →