Brown-out detection circuit
View Patent ↗A data processing system ( 100 ), such as a System-on-Chip, includes a processor ( 120 ), a memory ( 140 ) that has an expected minimum data retention voltage, and a brown-out detector ( 160 ), which includes a brown-out detection circuit ( 201 ) that has an analog output, and an output circuit ( 248 and 252 ) that converts the analog output of the brown-out detection circuit to a digital brown-out flag. The brown-out detection circuit includes a self-biased current reference, current mirrors, and a current comparator. The brown-out detector monitors voltage of a power supply of the memory, and the brown-out detector asserts the digital brown-out flag to the processor when the voltage of the power supply is at, or slightly above, a highest expected minimum data retention voltage.
1. A low-voltage detection circuit, comprising:
a voltage and current reference circuit for producing a reference current and a reference voltage;
a first resistive element having one end coupled to a first power supply voltage terminal;
a first transistor of a first conductivity type having a first current electrode coupled to another end of the first resistive element a second current electrode, and a control electrode connected to the second current electrode;
a second transistor of a second conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the voltage and current reference circuit, and a second current electrode coupled to a second power supply voltage terminal wherein the second transistor is configured to minor the reference current;
a third transistor of the first conductivity type having a first current electrode coupled to the first power supply voltage terminal, a second current electrode coupled to an output node, and a control electrode coupled to the control electrode of the first transistor; and
a fourth transistor of the second conductivity type having a first current electrode coupled to the output node, a control electrode coupled to the voltage and current reference circuit, and a second current electrode coupled to the second power supply voltage terminal, wherein the fourth transistor is configured to mirror the reference current,
wherein a voltage at the output node provides a low-voltage detection signal regarding a voltage at the first power supply voltage terminal.
2. The low-voltage detection circuit of claim 1 , wherein the third transistor is configured to minor the current through the first transistor.
3. The low-voltage detection circuit of claim 1 , wherein the voltage and current reference circuit is a self-biased voltage and current reference circuit.
4. The low-voltage detection circuit of claim 3 , wherein the voltage and current reference circuit includes:
a second resistive element having one end coupled to the first power supply voltage terminal, and
a fifth transistor of a second conductivity type having a first current electrode coupled to another end of the second resistive element, a control electrode connected to the first current electrode, and a second current electrode coupled to the second power supply voltage terminal, wherein the reference voltage is produced at the first current electrode, and wherein the reference current is a current through the fifth transistor.
5. The low-voltage detection circuit of claim 1 , wherein a channel width to channel length ratio (W/L) of the fourth transistor is larger than the W/L of the second transistor, and the low-voltage detection circuit is configured such that amount of current through the fourth transistor is the same as amount of current through the second transistor.
6. The low-voltage detection circuit of claim 1 , wherein a channel width to channel length ratio (W/L) of the fourth transistor is the same as the W/L of the second transistor, and low-voltage detection circuit is configured such that amount of current through the fourth transistor is the same as amount of current through the second transistor.
7. The low-voltage detection circuit of claim 6 , wherein the third transistor operates in triode region and the fourth transistor operates in saturation region, when the first power supply voltage terminal is above a low voltage condition, thereby producing a signal indicating a normal voltage condition.
8. The low-voltage detection circuit of claim 6 , wherein the third transistor operates in saturation region and the fourth transistor operates in triode region, when the first power supply voltage terminal is at or below a low voltage condition, thereby producing a signal indicating a low voltage condition.
9. An integrated circuit including a low-voltage detector, comprising:
a voltage and current reference circuit for producing a reference current and a reference voltage;
a first resistive element having one end coupled to a first power supply voltage terminal and having another end;
a first transistor of a first conductivity type having a first current electrode coupled to the other end of the first resistive element, a second current electrode, and a control electrode connected to the second current electrode;
a second transistor of a second conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the voltage and current reference circuit, and a second current electrode coupled to a second power supply voltage terminal;
a third transistor of the first conductivity type having a first current electrode coupled to the first power supply voltage terminal, a second current electrode coupled to an output node, and a control electrode coupled to the control electrode of the first transistor;
a fourth transistor of the second conductivity type having a first current electrode coupled to the output node, a control electrode coupled to the voltage and current reference circuit, and a second current electrode coupled to the second power supply voltage terminal; and
an output circuit coupled to the output node for providing a detection signal indicative of a voltage at the first power supply voltage terminal.
10. The integrated circuit of claim 9 , wherein the third transistor is configured to mirror the current through the first transistor.
11. The integrated circuit of claim 9 , wherein the second transistor and the fourth transistor is configured to minor the reference current.
12. The integrated circuit of claim 11 , wherein a current density of the second transistor is greater than a current density of the fourth transistor.
13. The integrated circuit of claim 9 , wherein the third transistor operates in triode region and the fourth transistor operates in saturation region, when the first power supply voltage terminal is above a low voltage condition, thereby producing a signal indicating a normal voltage condition.
14. The integrated circuit of claim 9 , wherein the third transistor operates in saturation region and the fourth transistor operates in triode region, when the first power supply voltage terminal is at or below a low voltage condition, thereby producing a signal indicating a low voltage condition.
15. A data processing system comprising:
a processor;
a memory, coupled to the processor, a first power supply voltage terminal and a second power supply voltage terminal, the memory having a brown-out voltage; and
a low-voltage detection circuit, coupled to the processor, the first power supply voltage terminal and the second power supply voltage terminal, the low-voltage detection circuit including:
a voltage and current reference circuit for producing a reference current and a reference voltage,
a first resistive element having one end coupled to a first power supply voltage terminal,
a first transistor of a first conductivity type having a first current electrode coupled to another end of the first resistive element, a second current electrode, and a control electrode connected to the second current electrode,
a second transistor of a second conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the voltage and current reference circuit, and a second current electrode coupled to a second power supply voltage terminal,
a third transistor of the first conductivity type having a first current electrode coupled to the first power supply voltage terminal, a second current electrode coupled to an output node, and a control electrode coupled to the control electrode of the first transistor, and
a fourth transistor of the second conductivity type having a first current electrode coupled to the output node, a control electrode coupled to the voltage and current reference circuit, and a second current electrode coupled to the second power supply voltage terminal, wherein a voltage at the output node indicates whether a voltage at the first power supply voltage terminal is at low voltage.
16. The data processing system of claim 15 , wherein the processor is coupled to receive a signal indicating a low voltage condition as detected by the low-voltage detection circuit.
17. The data processing system of claim 15 , wherein a channel width of the fourth transistor is larger than the channel width of the second transistor, wherein a channel length of the fourth transistor is the same as the channel length of the second transistor, and wherein the low-voltage detection circuit is configured such that amount of current through the fourth transistor is the same as amount of current through the second transistor.
18. The data processing system of claim 15 , wherein a channel width of the fourth transistor is the same as the channel width of the second transistor, wherein a channel length of the fourth transistor is the same as the channel length of the second transistor, and wherein the low-voltage detection circuit is configured such that amount of current through the fourth transistor is the same as amount of current through the second transistor.
19. The data processing system of claim 15 , wherein the third transistor operates in triode region and the fourth transistor operates in saturation region, when the first power supply voltage terminal is above the brown-out voltage, thereby producing an indication of a normal voltage condition.
20. The data processing system of claim 15 , wherein the third transistor operates in saturation region and the fourth transistor operates in triode region, when the first power supply voltage terminal is at or below the brown-out voltage, thereby producing an indication of a low voltage condition.