System and method to control one time programmable memory
View Patent ↗Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.
1. An integrated circuit comprising:
a hardware bus with more than one capability;
a first register to store at least one bit to allow a selected capability of the more than one capability to be disabled;
a one-time-programmable (OTP) memory to store the at least one bit, the OTP memory allowing the at least one bit to be written only once; and
logic to control the OTP memory, the logic operable to:
determine the at least one bit based on a functionality of the hardware bus;
store the at least one bit in the first register; and
set the at least one bit in the OTP memory.
2. The integrated circuit of claim 1 , further comprising a second register to store lock bits, the lock bits indicating capability bits that have been written once to the OTP memory.
3. The integrated circuit of claim 1 , wherein the OTP memory further comprises multiple OTP memory banks and wherein at least a portion of one of the OTP memory banks is dedicated for storage of a cryptographic key.
4. The integrated circuit of claim 3 , wherein the cryptographic key is stored in the at least a portion of one of the OTP memory banks after the integrated circuit has left control of a manufacturer of the integrated circuit.
5. The integrated circuit of claim 1 , wherein the OTP memory further comprises multiple random accessible output pins, each random accessible output pin corresponding to a unique memory address in the OTP memory, wherein the multiple random accessible output pins are input into a multiplexing circuit, and wherein an output of the multiplexing circuit has a bit width that is less than a number of the multiple random accessible output pins.
6. The integrated circuit of claim 5 , wherein the OTP memory further comprises a serial output port that allows random access to each unique memory address in the OTP memory.
7. The integrated circuit of claim 6 , wherein there are 256 random accessible output pins and the bit width is 32.
8. An integrated circuit, comprising:
at least one register;
a one-time-programmable (OTP) memory bank;
logic operable to:
disable at least one capability in the integrated circuit by setting at least one bit in the OTP memory bank; and
copy bits of the OTP memory bank to the at least one register when the OTP memory bank is not read-enabled.
9. The integrated circuit of claim 8 , further comprising logic to set a corresponding lock bit when the at least one bit has been written once to the OTP memory bank.
10. The integrated circuit of claim 8 , wherein the at least one bit is set after the integrated circuit has shipped from a manufacturer.
11. The integrated circuit of claim 8 , further comprising a second OTP memory bank that is dedicated to store a cryptographic key.
12. The integrated circuit of claim 8 , wherein the at least one bit is allowed to be set until a lock bit is set.
13. The integrated circuit of claim 8 , wherein the logic is operable to set the at least one bit in the OTP memory bank when a clock of the OTP memory bank has been set to a frequency, when a first voltage in the OTP memory bank has been raised to a first level, and when the OTP memory bank is not in a read state.
14. The integrated circuit of claim 13 , wherein the first level comprises a voltage level that is greater than an operating voltage of the OTP memory bank, the operating voltage for reading data from the OTP memory bank.
15. The integrated circuit of claim 8 , wherein the at least one register includes a first register and a second register, the first register to store a memory address for a write operation, the second register to store a copy of the memory address, and wherein modification of the copy is prevented until the write operation is complete.
16. The integrated circuit of claim 8 , wherein the at least one register is writeable until a first lock bit in the OTP memory bank is set.
17. The integrated circuit of claim 16 , wherein the first lock bit is writeable until a second lock bit in a lock register is set.
18. The integrated circuit of claim 8 , further comprising logic to set an error bit when a second read operation on the OTP memory bank is attempted while a first read or write operation is being performed upon the OTP memory bank.
19. An integrated circuit, comprising:
a processor;
a one-time-programmable (OTP) memory bank;
a hardware capability bus;
logic operable to:
determine a functionality for the hardware capability bus;
disable the functionality by setting at least one bit in the OTP memory bank; and
copy information of the OTP memory bank to registers that are accessible by the processor when the OTP memory bank is not read-enabled.
20. The integrated circuit of claim 19 , further comprising logic operable to:
determine when a lock bit has been set; and
prevent setting the at least one bit in the OTP memory bank when the lock bit has been set.