Granted Patent B2

US 8,310,300 · App. 12/870,464 · Granted Nov 13, 2012

Abstract

Claims (55)

1. A charge pump comprising:

a first counter having a control input for receiving a control signal, and an output for providing a first count value, wherein the first count value is incremented in response to the control signal being a first logic state and the first count value is decremented in response to the control signal being a second logic state;

a pump stage having a variable capacitor, the variable capacitor having a control input coupled to the output of the first counter for receiving the first count value, wherein a capacitance value of the variable capacitor is changed in response to the first count value changing, and wherein the capacitance value is for determining a ramp-up rate of an output voltage at an output of the charge pump;

a second counter having an output for providing a second count value;

a digital-to-analog converter having an input coupled to the output of the second counter, and an output for providing an analog representation of the second count value;

a comparator having a first input coupled to the output of the digital-to-analog converter, a second input coupled to the output of the charge pump, and an output for providing the control signal to the control input of the first counter; and

a switch coupled between the output of the second counter and the input of the digital-to-analog converter, the switch having a control input for receiving a first clock signal.

2. The charge pump of claim 1 , further comprising:

a register for storing a digital value corresponding to a desired output voltage at the output of the charge pump, the register having an output selectively coupled to the input of the digital-to-analog converter;

wherein the switch alternately couples the second count value and the digital value to the input of the digital-to-analog converter in response to the first clock signal.

3. The charge pump of claim 2 , further comprising:

a first flip-flop having an input coupled to the output of the comparator, an output coupled to the control input of the variable capacitor, and a clock input for receiving a second clock signal; and

a second flip-flop having an input coupled to the output of the comparator, an output coupled to the pump stage, and a clock input for receiving a third clock signal.

4. The charge pump of claim 3 , wherein the second clock signal and the third clock signal are characterized as being non-overlapping clock signals.

5. The charge pump of claim 3 , wherein the first flip-flop responds to rising edges of the second clock signal and second flip-flop responds to rising edges of the third clock signal.

6. The charge pump of claim 1 , wherein the first counter comprises:

a first register for storing an interval value, the first register having an output;

an adder having a first input coupled to the output of the first register, a second input, a control input, and an output; and

a second register having in input coupled to the output of the adder, and an output coupled to the second input of the adder.

7. The charge pump of claim 1 , wherein the charge pump is implemented on a single integrated circuit.

8. A charge pump comprising:

a first counter having an output for providing a first count value;

a digital-to-analog converter having an input coupled to the output of the first counter, and an output for providing an analog representation of the first count value;

a comparator having a first input coupled to the output of the digital-to-analog converter, a second input, and an output;

a second counter having an input coupled to the output of the comparator, and an output for providing a second count value;

a pump stage having an input, an output coupled to the second input of the comparator, and a variable capacitor, a capacitance value of the variable capacitor being changed in response to the second count value;

wherein the first counter comprises:

a first register having an output;

an adder having a first input coupled to the output of the first register, a second input, and an output; and

a second register having an input coupled to the output of the adder, and an output coupled to the second input of the adder;

wherein the second counter comprises:

a third register having an output

an adder/subtractor having a first input coupled to the output of the third register, a second input, and an output;

a fourth register having an input coupled to the output of the adder/subtractor, and an output coupled to the second input of the adder/subtractor; and

a fifth register for storing a digital value corresponding to a desired output voltage at the output of the pump stage, wherein the digital value and the first count value are alternately provided to the input of the digital-to-analog converter.

9. The charge pump of claim 8 , further comprising a switch, the switch for alternately coupling the output of the second register and an output of the fifth register to the input of the digital-to-analog converter in response to a clock signal.

10. The charge pump of claim 8 , further comprising a first logic circuit coupled between the output of the comparator and the input of the second counter.

11. The charge pump of claim 8 , wherein the charge pump is implemented in a single integrated circuit.

12. A charge pump comprising:

a first counter having an output for providing a first count value;

a digital-to-analog converter having an input and an output;

a first register for storing a digital value corresponding to a desired output voltage at an output of the charge pump;

a switch having a first terminal coupled to the output of the first register, a second terminal coupled to the output of the first counter, and a third terminal coupled to the input of the digital-to-analog converter, wherein the digital value and the first count value are alternately provided to the input of the digital-to-analog converter in response to a clock signal;

a comparator having a first input coupled to the output of the digital-to-analog converter, a second input, and an output;

a second counter having an input coupled to the output of the comparator, and an output for providing a second count value; and

a pump stage having a variable capacitor, the variable capacitor having an input coupled to the output of the second counter for receiving the second count value, the pump stage having an output coupled to the second input of the comparator, the pump stage having a clock input coupled to the output of the comparator.

13. The charge pump of claim 12 , wherein the second counter is an up/down counter, wherein the up/down counter increments the second count value in response to the output of the comparator being a first logic state, and the up/down counter decrements the second count value in response to the output of the comparator being a second logic state.

14. The charge pump of claim 12 , wherein the first counter comprises:

a first register having an output;

an adder having a first input coupled to the output of the first register, a second input, and an output; and

a second register having an input coupled to the output of the adder, and an output coupled to the second input of the adder.

15. The charge pump of claim 12 , wherein the second counter comprises:

a first register having an output;

an adder/subtractor having a first input coupled to the output of the first register, a second input, and an output; and

a second register having an input coupled to the output of the adder/subtractor, and an output coupled to the second input of the adder/subtractor.

Assignments (21)