Hierarchical error correction for large memories
View Patent ↗A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access.
1. A method comprising:
determining presence of data errors for each of a plurality of unique memory segments of a memory region;
for each memory segment if the data error is a first type of error, correcting the data error in the memory segment, wherein the first type of error has no more than a first number of bit errors;
for each memory segment if the data error is a second type of error, set a flag associated with the memory segment, wherein the second type of error has a second number of bit errors that is greater than the first number of bit errors; and
if only one memory segment in the memory region has its associated flag set, then determining if the data error is a third type of error, and in response to the data error not being the third type of error correcting the data error in the only one memory segment for the memory region, otherwise, determine a corrective action, wherein the third type of error has a third number of bit errors that is greater than the second number of bit errors.
2. The method of claim 1 wherein the memory region comprises a cache line of a cache memory.
3. The method of claim 2 wherein the memory segment comprises a double word.
4. The method of claim 2 further comprising:
if a plurality of flags are set corresponding to a plurality of memory segments, then
reloading the cache line from a corresponding system memory location, if the cache line is not dirty, and
rebooting a system comprising the cache memory if the cache line is dirty.
5. The method of claim 2 further comprising:
if the data error is the third type of error, then
reloading the cache line from a corresponding system memory location, if the cache line is not dirty, and
rebooting a system comprising the cache memory if the cache line is dirty, wherein the third type of error comprises errors in at least three bits of the memory segment.
6. The method of claim 1 wherein the first type of error comprises a single bit error in the memory segment.
7. The method of claim 6 wherein said correcting the data error in the memory segment comprises:
executing a single bit error correction Hamming code using parity bits associated with the memory segment.
8. The method of claim 7 , wherein
the second type of error comprises a double bit error in the memory segment, and
said executing the Hamming code further determines the presence of the second type of error.
9. The method of claim 8 wherein said correcting the second type of error comprises:
executing a double bit error correction code using parity bits associated with the memory region and an identification of the flagged memory segment.
10. The method of claim 1 further comprising:
storing the memory segments in the memory region by interleaving bits from each memory segment.
11. A memory subsystem comprising:
a data memory storing data in one or more memory regions, wherein each memory region comprises a plurality of unique memory segments; and
an error control circuit, coupled to the data memory, and comprising
a first level error detection and correction logic configured to
determine a presence of data errors for each segment of a memory region, and
for each memory segment, if the data error is a first type of error correct the data error in the memory segment, wherein the first type of error has no more than a first number of bit errors, and if the data error is a second type of error set a flag associated with the memory segment, wherein the second type of error has a second number of bit errors that is greater than the first number of bit errors, and
a second level error detection and correction logic configured to
determine that the data error is a third type of error when only one memory segment has its associated flag set, and
correct the data error for the memory region in response to the data error not being the third type of error, otherwise determine a corrective action, wherein the third type of error has a third number of bit errors that is greater than the second number of bit errors.
12. The memory subsystem of claim 11 wherein the error control circuit further comprises:
an error detection and correction circuit comprising the first level and second level error detection and correction logics.
13. The memory subsystem of claim 11 wherein the error control circuit further comprises:
an error correction encoder circuit configured to
generate one or more first level parity bits for each segment of a memory region for use by the first level error detection and correction logic, and
generate one or more second level parity bits for each memory region for use by the second level error detection and correction logic; and
the data memory storing the first level and second level parity bits in association with the corresponding memory region.
14. The memory subsystem of claim 13 wherein the error correction circuit is further configured to generate the first level and second level parity bits when data to be stored in the memory region is received at the memory subsystem.
15. The memory subsystem of claim 11 wherein the error control circuit is configured to perform said determining the presence of data errors when the data stored in a memory region is accessed.
16. The memory subsystem of claim 11 wherein the first level error detection and correction logic is further configured to:
perform a single bit error correction Hamming code, wherein
the first type of error comprises a single bit error in the memory segment, and
the second type of error comprises a double bit error in the memory segment.
17. The memory subsystem of claim 11 wherein the second level error detection and correction logic is further configured to:
perform a double bit error correction polynomial code, wherein
the third type of error comprises a triple bit error in the memory region.
18. The memory subsystem of claim 11 further comprising:
the data memory configured to store the memory segments in the memory region by interleaving bits from each memory segment.
19. The memory subsystem of claim 11 wherein the memory subsystem is a multi-way cache memory subsystem, the memory subsystem further comprising:
the data memory configured to store the memory regions by interleaving corresponding bits of a memory region from a plurality of ways.
20. A cache memory subsystem comprising:
a data memory storing data in one or more cache lines, wherein each cache line comprises a plurality of unique double word segments; and
an error control circuit, coupled to the data memory, and comprising
a first level error detection and correction logic configured to
determine a presence of data errors for each double word segment of a cache line when data from the cache line is accessed, and
for each double word segment, if the data error is a single bit error then correct the single error in the double word segment, and if the data error is a two or more bit error then set a flag associated with the double word segment, and
a second level error detection and correction logic configured to
determine that the data error is a triple bit error in the cache line when only one double word segment has its associated flag set, and
correct the data error for the memory region in response to the data error not being a triple bit error, otherwise determine a corrective action.