Device having conductive substrate via with catch-pad etch-stop
View Patent ↗An electronic device ( 50 ) having a conductive substrate via ( 70 ) extending between a conductor ( 39 ) on a rear face ( 22 ) and a conductor ( 58 ) over the front surface ( 23 ) of the substrate ( 21 ) includes a multi-layered etch-stop ( 56, 56 - 2 ) beneath the front surface conductor ( 58 ). The etch-stop ( 56, 56 - 2 ) permits use of a single etchant to penetrate both the substrate ( 21 ) and any overlying semiconductor ( 44 ) and/or dielectric ( 34 ) without attacking the overlying front surface conductor ( 58 ). This is especially important when the semiconductor ( 44 ) and dielectric ( 34 ) are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop ( 56 ) is preferably a stack ( 63, 73 ) of N≧2 pairs ( 62 - i ) of sub-layers ( 62 - i 1, 62 - i 2 ) in either order, where a first sub-layer ( 62 - i 1 ) comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer ( 62 - i 2 ) comprises etch resistant material (e.g., Ni). In a further embodiment, where the device ( 50 ) includes field effect transistors ( 52 ) having feedback sensitive control gates ( 30 ), the etch-stop material ( 56 ) is advantageously used to form gate shields ( 76 ).
1. An electronic device having a substrate with a conductive through-substrate via extending between a first surface and a second surface of the substrate, comprising:
a front surface conductor above the second surface;
a multi-layered etch-stop region electrically coupled to the front surface conductor, wherein the multi-layered etch-stop region is resistant to an etchant that etches the substrate; and
a via conductor extending at least from the first surface of the substrate through the substrate and making electrical contact via the multi-layered etch-stop region to the front surface conductor, thereby forming the through-substrate conductive via;
wherein the multi-layered etch-stop region comprises a multiplicity of layer pairs, each layer pair comprising a first sub-layer of a stress relief or adhesion promoting material and a second sub-layer of an etch resistant material, arranged in either order.
2. The electronic device of claim 1 , wherein the multi-layered etch-stop region comprises a stack of 2≦N≦10 pairs of sub-layers.
3. The electrical device of claim 1 , wherein the multi-layered etch stop region lies between the front surface conductor and the second surface.
4. The electronic device of claim 1 , wherein the multi-layered etch-stop region comprises a stack of N≧2 pairs of sub-layers and further comprising a corrosion resistant layer overlying the stack of N≧2 pairs of sub-layers.
5. The electronic device of claim 4 , further comprising an adhesion layer between the stack of N≧2 pairs of sub-layers and the corrosion resistant layer.
6. The electronic device of claim 4 , wherein the stress relief or adhesion promoting material sub-layer comprises at least one of the group consisting of titanium, chromium, tantalum, and combinations thereof, and the etch resistant material sub-layer comprises at least one of the group consisting of nickel, aluminum, indium-tin-oxide, and combinations thereof.
7. The electronic device of claim 1 , wherein the electronic device comprises a field effect transistor having a gate with a gate shield formed from the same material as the multi-layered etch-stop region.
8. An electronic device, comprising:
a substrate having a first conductor on a rear surface thereof and a second conductor over a front surface thereof;
an electrically conductive multi-layered etch-stop located between a portion of the front surface of the substrate and the second conductor;
a substrate via extending through the substrate from the rear surface thereof to the multi-layered etch-stop; and
a third conductor in the substrate via electrically coupling the first conductor to the second conductor via the multi-layered etch stop;
wherein the electrically conductive multi-layered etch-stop comprises a stack of N≧2 double layers, each double layer comprising a first sub-layer of an adhesion or stress relief or both promoting conductor and a second sub-layer of an etch resistant conductor, arranged in either order.
9. The device of claim 8 , wherein the second sub-layer comprises at least one of the group consisting of Ni, Al, In—Sn oxide, and combinations thereof.
10. The device of claim 8 , further comprising an oxidation resistant layer between the electrically conductive multi-layered etch-stop and the second conductor.
11. An electronic device, comprising:
a substrate having an upper surface and a lower surface;
a semiconductor layer formed over the upper surface of the substrate;
a dielectric layer formed over the semiconductor layer;
a catch-pad conductor formed over the dielectric layer;
a multi-layered etch-stop region formed over the dielectric layer and electrically coupled to the catch-pad conductor; and
a through-substrate via extending from the lower surface of the substrate, through the semiconductor layer, through the dielectric layer, and to the multi-layered etch stop region, the through-substrate via electrically coupled to the catch-pad conductor through the multi-layered etch stop region.
12. The electronic device of claim 11 , further comprising at least one transistor formed over the substrate, and wherein the semiconductor layer has a first thickness proximate the at least one semiconductor device and a second thickness proximate the through-substrate conductive via, the first thickness greater than the second thickness.
13. The electronic device of claim 12 , wherein the second thickness is about 0.2 to about 0.3 micrometers less than the first thickness.
14. The electronic device of claim 11 , wherein the multi-layered etch stop region comprises multiple layers of an etch resistant material.
15. The electronic device of claim 14 , wherein the semiconductor layer comprises gallium nitride, wherein the dielectric layer comprises silicon nitride, and wherein the etch resistant material is selected form the group consisting of nickel, aluminum, indium-tin oxide, and combinations thereof.
16. The electronic device of claim 11 , wherein the multi-layered etch-stop region comprises multiple layers of a stress relief or adhesion promoting material.
17. The electronic device of claim 16 , wherein the semiconductor layer comprises gallium nitride, wherein the dielectric layer comprises silicon nitride, and wherein the stress relief or adhesion promoting material is selected from the group consisting of titanium, chromium, tantalum, and combinations thereof.
18. The electronic device of claim 11 , wherein the multi-layered etch-stop region comprises:
at least two etch resistant layers; and
at least one layer of a stress relief or adhesion promoting material interspersed with the at least two etch resistant layers.
19. The electronic device of claim 11 , wherein the multi-layered etch-stop region comprises:
at least one layer pair comprising a first layer of an etch resistant material and a second layer of a stress relief or adhesion promoting material; and
a capping layer formed over the at least one layer pair.
20. The electronic device of claim 11 , wherein the catch-pad conductor has a width greater than the width of the through-substrate via, as taken along the upper surface of the substrate.