Cache locking control
View Patent ↗Each cache line of a cache has a lockout state that indicates whether an error has been detected for data accessed at the cache line, and also has a data validity state, which indicates whether the data stored at the cache line is representative of the current value of data stored at a corresponding memory location. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. In response to a cache invalidation event, the state of the lockout indicators for each cache line can be maintained so that locked out cache lines remain in the locked out state even after a cache invalidation. This allows memory error management software executing at the data processing device to robustly manage the state of the lockout indicators.
1. In a data processing device comprising a processor unit coupled to a cache comprising a plurality of cache lines, a method comprising:
setting a lockout indicator in response to detecting an error at data stored at a first cache line of the plurality of cache lines;
determining a lockout policy based on stored information;
in response to determining the lockout policy is a first policy, maintaining the lockout indicator for the first cache line in the first state in response to a cache invalidation event; and
in response to determining the lockout policy is a second policy, setting the lockout indicator for the first cache line to a second state in response to the cache invalidation event.
2. The method of claim 1 , wherein the first cache line is not employed to satisfy cache accesses when the lockout indicator is in the first state.
3. The method of claim 2 , wherein the first cache line is employed to satisfy cache accesses when the lockout indicator is in the second state.
4. The method of claim 1 , wherein the cache invalidation event comprises execution of an instruction to invalidate the cache at the processor unit.
5. The method of claim 1 , wherein the cache invalidation event comprises a reset event at the processor unit.
6. The method of claim 1 , further comprising:
when the lockout policy is the first policy, setting the lockout indicator for the first cache line to the second state in response to a software request, wherein the first cache line is employed to satisfy cache accesses when the lockout indicator is in the second state.
7. The method of claim 1 , wherein detecting the error comprises detecting the error based on a set of ECC checkbits associated with data stored at the first cache line.
8. The method of claim 1 , further comprising determining the lockout policy based on information stored at a register.
9. The method of claim 8 , further comprising maintaining the information stored at the register in response to the cache invalidation event when the information stored at the register indicates the lockout policy is the first policy.
10. A method, comprising:
in response to an indication of a cache invalidation event at a data processing device, determining a lockout reset policy for a cache based on stored information;
in response to determining the lockout reset policy is a first policy, placing a plurality of lockout indicators in a reset state;
in response to determining the lockout reset policy is a second policy, maintaining the plurality of lockout indicators in a current state; and
preventing indication of a cache hit at a cache line based on a first lockout indicator of the plurality of lockout indicators.
11. The method of claim 10 , comprising resetting the lockout policy to a reset state in response to the indication of the cache invalidation event.
12. The method of claim 11 , wherein the reset state of the lockout policy indicates the second policy.
13. The method of claim 10 , further comprising setting the first lockout indicator to a locked-out state in response to detecting an error at data stored at a cache line associated with the first lockout indicator, the cache prevented from indicating a cache hit at the cache line when the first lockout indicator is in the locked-out state.
14. The method of claim 10 , further comprising determining the lockout policy based on information stored at a register.
15. A device, comprising:
a processor unit;
a cache comprising a plurality of cache lines; and
a cache control module that sets a lockout indicator in response to detecting an error at data stored at a first cache line of the plurality of cache lines, wherein the lockout module includes a cache reset module that:
in response to determining a lockout policy is a first policy, maintains the lockout indicator for the first cache line in the first state in response to a cache invalidation event, determining the lockout policy based on stored information; and
in response to determining the lockout policy is a second policy, sets the lockout indicator for the first cache line to a second state in response to the cache invalidation event.
16. The device of claim 15 , wherein the cache control module does not employ the first cache line to satisfy cache accesses when the lockout indicator is in the first state.
17. The device of claim 16 , wherein the cache control module employs the first cache line to satisfy cache accesses when the lockout indicator is in the second state.
18. The device of claim 15 , wherein the cache control module, when the lockout policy is the first policy, sets the lockout indicator for the first cache line to the second state in response to a software request.
19. The data processing device of claim 15 , wherein the cache invalidation event comprises execution of an instruction to invalidate the cache at the processor unit.
20. A device of claim 15 , further comprising determining the lockout policy based on information stored at a register.