Circuit for verifying the write enable of a one time programmable memory
View Patent ↗A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.
1. A memory system comprising:
a one time programmable (OTP) memory; and
a write enable verification circuit coupled to the OTP memory including a first inverter stage and a second inverter stage coupled at a node, wherein the write enable verification circuit is configured to receive a write enable signal, and wherein when the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate, and wherein the write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.
2. The memory system of claim 1 , wherein the second voltage level is greater than the first voltage level.
3. The memory system of claim 1 further comprising a capacitor having a first terminal coupled to the node and a second terminal coupled to a voltage supply terminal.
4. The memory system of claim 1 , wherein the first inverter stage comprises:
a p-channel transistor having a first current terminal coupled to a first voltage supply terminal, a control terminal coupled to receive the write enable signal, and a second current terminal coupled to the node;
a first n-channel transistor having a first current terminal coupled to the node, a control terminal coupled to receive the write enable signal, and a second current terminal; and
a second n-channel transistor having a first current terminal coupled to the second current terminal of the first n-channel transistor, a control terminal coupled to a second voltage supply terminal, and a second current terminal coupled to a third voltage supply terminal, wherein a first voltage at the first voltage supply terminal is greater than a second voltage at the second voltage supply terminal, and wherein the second voltage is greater than a third voltage at the third voltage supply terminal.
5. The memory system of claim 4 , wherein the second inverter stage comprises:
a p-channel transistor having a first current terminal coupled to the first voltage supply terminal, a control terminal coupled to the node, and a second current terminal coupled to a node for providing an asymmetrically delayed write enable signal; and
a n-channel transistor having a first current terminal coupled to the node for providing the asymmetrically delayed write enable signal, a control terminal coupled to the node, and a second current terminal coupled to the third voltage supply terminal.
6. The memory system of claim 5 , wherein the write enable verification circuit further comprises a logical AND gate: (1) for receiving the asymmetrically delayed write enable signal and the write enable signal and (2) for providing the verified write enable signal.
7. The memory system of claim 1 , wherein the OTP memory comprises a plurality of eFuses, and wherein the memory system further comprises an OTP controller, wherein the OTP controller is configured to receive the verified write enable signal and maintain the write enable signal at the second voltage level for a specified time sufficient for programming at least one of the plurality of eFuses.
8. A memory system comprising:
a one time programmable (OTP) memory;
an OTP controller coupled to the OTP memory, wherein the OTP controller is configured to generate a write enable signal; and
a write enable verification circuit coupled to the OTP memory and the OTP controller, wherein the write enable verification circuit is configured to receive the write enable signal from the OTP controller, and wherein the write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory by the OTP controller.
9. The memory system of claim 8 , wherein the OTP memory comprises a plurality of eFuses, and wherein the OTP controller is further configured to receive the verified write enable signal and in response to receiving the verified write enable signal maintain the write enable signal at a certain voltage level for a specified time sufficient for programming at least one of the plurality of eFuses.
10. The memory system of claim 8 , wherein the write enable verification circuit comprises an asymmetric delay circuit configured to delay the write enable signal.
11. The memory system of claim 10 , wherein the asymmetric delay circuit comprises a first inverter stage and a second inverter stage, wherein an output of the first inverter stage and an input of the second inverter stage are coupled at a node.
12. The memory system of claim 11 , wherein when the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate.
13. The memory system of claim 11 , wherein the first inverter stage comprises:
a P-channel transistor having a first current terminal coupled to a first voltage supply terminal, a control terminal coupled to receive the write enable signal, and a second current terminal coupled to the node;
a first N-channel transistor having a first current terminal coupled to the node, a control terminal coupled to receive the write enable signal, and a second current terminal; and
a second N-channel transistor having a first current terminal coupled to the second current terminal of the first n-channel transistor, a control terminal coupled to a second voltage supply terminal, and a second current terminal coupled to a third voltage supply terminal, wherein a first voltage at the first voltage supply terminal is greater than a second voltage at the second voltage supply terminal, and wherein the second voltage is greater than a third voltage at the third voltage supply terminal.
14. The memory system of claim 13 , wherein the second inverter stage comprises:
a p-channel transistor having a first current terminal coupled to the first voltage supply terminal, a control terminal coupled to the node, and a second current terminal coupled to a node for providing an asymmetrically delayed write enable signal; and
a n-channel transistor having a first current terminal coupled to the node for providing the asymmetrically delayed write enable signal, a control terminal coupled to the node, and a second current terminal coupled to the third voltage supply terminal.
15. The memory system of claim 14 , wherein the write enable verification circuit further comprises a logical AND gate: (1) for receiving the asymmetrically delayed write enable signal and the write enable signal and (2) for providing the verified write enable signal.
16. A memory system comprising:
a one time programmable (OTP) memory; and
a write enable verification circuit coupled to the OTP memory, wherein the write enable verification circuit is configured to receive an input signal, and wherein the write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory, wherein the write enable verification circuit comprises:
a first inverter stage having an input coupled to receive the input signal and an output coupled to provide a switching voltage signal, and
a second inverter stage having an input coupled to receive the switching voltage signal and an output coupled to provide an output signal, and wherein the first inverter stage and the second inverter stage are configured such that the second inverter stage switches the output from a first voltage level to a second voltage level different from the first voltage level only when the input signal is maintained at a predetermined level for at least a predetermined time.
17. The memory system of claim 16 further comprising a logical AND gate: (1) for receiving the output signal of the second inverter stage and the input signal and (2) for providing the verified write enable signal.
18. The memory system of claim 17 , wherein the switching voltage signal at the input of the second inverter stage is initially set at a first voltage signal level, and wherein the switching voltage signal changes from the first voltage signal level to a second voltage signal level sufficient to switch the output of the second inverter stage from the first voltage level to the second voltage level only when the input signal is maintained at the predetermined level for at least the predetermined time.
19. The memory system of claim 16 , wherein a plurality of spurious write enable signals are received as the input signal and wherein the first inverter stage and the second inverter stage are configured such that the second inverter stage never switches the output from the first voltage level to the second voltage level different from the first voltage level regardless of how many of the plurality of spurious write enable signals are received as the input signal.
20. The memory system of claim 16 , wherein the first inverter stage and the second inverter stage are configured such that when the input signal transitions from a first input voltage level to a second input voltage level, the switching voltage signal changes from a first switching voltage level to a second switching voltage level in a first time period, and wherein when the input signal transitions from the second input voltage level to the first input voltage level, the switching voltage signal changes from the second switching voltage level to the first switching voltage level in a second time period, wherein the first time period is at least 100 times greater than the second time period.