Data transfer coherency device and methods thereof
View Patent ↗Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.
1. A device, comprising:
a bus interface module comprising an input coupled to an address bus, an input coupled to a first data bus, and a plurality of enable outputs;
a first data latch comprising an input coupled to the first data bus, and an output coupled to a second data bus;
a first plurality of coherent access registers, each of the plurality of coherent access registers comprising a first input coupled to the second data bus, a second input coupled to a third data bus, and a first enable input coupled to a corresponding one of the plurality of enable outputs to simultaneously latch data at the output of the first data latch and on the third data bus at the corresponding coherent access register; and
wherein the bus interface module further comprises:
a second data latch comprising an input coupled to a fourth data bus, and an output; and
a signal select multiplexer comprising a first input coupled to the output of the second data latch and an output coupled to the first data bus.
2. The device of claim 1 , wherein the bus interface module comprises an address latch having a plurality of input nodes coupled to the address bus and an output.
3. The device of claim 2 , wherein the bus interface module further comprises a first comparator comprising a first input coupled to the address bus, a second input coupled to the output of the address latch, and an output.
4. The device of claim 3 , wherein the bus interface module further comprises a second comparator comprising a first input coupled to the address bus and an output.
5. The device of claim 1 , wherein the signal select multiplexer further comprises a second input coupled to the fourth data bus, a third input coupled to a fifth data bus, and a control input.
6. The device of claim 5 , wherein the first enable input at each of the plurality of coherent access registers is to provide a first portion of the data at the corresponding coherent access register to the second data latch and to simultaneously provide a second portion of the data to the fifth data bus.
7. The device of claim 5 , further comprising a buffer coupled between the output of the signal select multiplexer and the first data bus.
8. The device of claim 1 , wherein a coherent access register of the first plurality of data access registers is twice the size of the first data bus.
9. The device of claim 1 , wherein the bus interface module comprises a first integrated circuit and the first plurality of coherent access registers comprise a second integrated circuit.
10. A device, comprising:
a bus interface module comprising an input coupled to an address bus, an input coupled to a first data bus, a signal select multiplexer comprising a first input and an output coupled to the first data bus, and a plurality of enable outputs;
a first data latch comprising an output coupled to the first input of the signal select multiplexer, and an input coupled to a second data bus;
a first plurality of coherent access registers, each of the plurality of coherent access registers comprising a first output coupled to the second data bus, a second output coupled to a third data bus, and a first enable input coupled to a corresponding one of the plurality of enable outputs to simultaneously provide data at the first output and the second output of the corresponding access register on the second data bus.
11. The device of claim 10 , wherein the bus interface module comprises an address latch having a plurality of input nodes coupled to the address bus and an output.
12. The device of claim 11 , wherein the bus interface module further comprises a first comparator comprising a first input coupled to the address bus, a second input coupled to the output of the address latch, and an output.
13. The device of claim 12 , wherein the bus interface module further comprises a second comparator comprising a first input coupled to the address bus and an output.
14. The device of claim 10 , wherein the signal select multiplexer further comprises a second input coupled to the second data bus, a third input coupled to the third data bus, and a control input.
15. The device of claim 14 , wherein the first enable input at each of the plurality of coherent access registers is to provide a first portion of the data at the corresponding coherent access register to the second data bus and to simultaneously provide a second portion of the data to the third data bus.
16. The device of claim 14 , further comprising a buffer coupled between the output of the signal select multiplexer and the first data bus.
17. The device of claim 10 , wherein a coherent access register of the first plurality of data access registers is twice the size of the first data bus.
18. The device of claim 10 , wherein the bus interface module comprises a first integrated circuit and the first plurality of coherent access registers comprise a second integrated circuit.