Low voltage detector
A low voltage detector ( 100 ) includes a power supply voltage monitor circuit ( 110 ) that produces a voltage V SP related to a first a power supply voltage, and a voltage generator ( 105 ), which includes a plurality of self-cascode MOSFET (SCM) structures ( 101 - 103 ) in a cascade configuration, that generates a reference voltage V xm . A voltage comparator ( 140 ) outputs an output signal in response to a differential between V xm and V SP , wherein V xm and V SP have proportional to absolute temperature behavior (PTAT) over temperature with respect to a second power supply voltage. The output signal changes state when the first power supply voltage equals a trip point of the comparator. Each SCM structure is sized to provide a rate of change with temperature of the PTAT behavior of V xm that matches a rate of change with temperature of the PTAT behavior of V SP .
1. A low voltage detector including terminals for coupling to a first power supply terminal and to a second power supply terminal of a power supply, the low voltage detector comprising:
a power supply voltage monitor circuit for monitoring a voltage at the first power supply terminal and for producing a voltage V sp related to the voltage at the first power supply terminal, the power supply voltage monitor circuit having a temperature variation coefficient;
a voltage generator, for generating a reference voltage V xm related to a voltage at the second power supply terminal, the voltage generator including a single array of a plurality of self-cascode MOSFET (SCM) structures arranged in a cascade configuration, the voltage generator having a temperature variation coefficient that is similar to the temperature variation coefficient of the power supply voltage monitor circuit; and
a voltage comparator, having a first comparator input coupled to the power supply voltage monitor circuit for coupling the voltage V SP to the first comparator input, and having a second comparator input coupled to the voltage generator for coupling the voltage V xm to the second comparator input, the voltage comparator for outputting a low voltage detect output signal in response to a differential voltage between V xm and V SP , wherein the voltages V xm and V sp have a substantially same voltage rate of change and in a same direction with respect to temperature based on the similar temperature variation coefficient of the power supply voltage monitor circuit and the voltage generator, wherein the low voltage detect output signal changes state when the voltage V SP equals the voltage V xm .
2. The low voltage detector of claim 1 , in which each SCM structure of the plurality of SCM structures includes a first NMOS transistor and a second NMOS transistor, wherein a drain terminal of the first transistor and a source terminal of the second transistor are connected together, wherein a gate terminal of the first transistor is connected to a gate terminal of the second transistor, and wherein the drain terminal of the first transistor receives a current coming from an adjacent SCM, and in which the gate and drain terminals of the second transistor of each SCM structure of the plurality of SCM structures are connected together and are coupled to a separate current source.
3. The low voltage detector of claim 2 , in which the first transistor and the second transistor of each SCM structure of the plurality of SCM structures are sized to provide a rate of change with temperature of V xm that matches a rate of change with temperature of V SP .
4. The low voltage detector of claim 2 , in which the first transistor of each SCM structure of the plurality of SCM structures operates in a linear region and the second transistor of each SCM structure of the plurality of SCM structures operates in a saturated region, and in which the first transistor and the second transistor are biased to operate in moderate to strong inversion.
5. The low voltage detector of claim 2 , in which the plurality of SCM structures includes a first SCM structure in which the first transistor of the first SCM structure has its source terminal coupled to the second power supply terminal, and at least a second SCM structure, and in which the first transistor of the second SCM structure has its source terminal coupled to a node of the first SCM structure at which a drain terminal of the first transistor and a source terminal of the second transistor of the first SCM are connected together.
6. The low voltage detector of claim 2 , in which the power supply voltage monitor circuit includes a PMOS transistor having a source terminal coupled to the first power supply terminal, having a drain terminal coupled to the voltage comparator, and having a gate terminal coupled to the drain terminal and to a current sink, the current sink for providing a bias current for the PMOS transistor, and in which V SP is a voltage at the drain terminal.
7. The low voltage detector of claim 6 , in which a source-to-drain voltage drop in the PMOS transistor is an absolute value of a PMOS threshold voltage V thP , and in which V SP ≈V DD −|V thP |.
8. The low voltage detector of claim 1 , in which the power supply voltage monitor circuit includes a diode having an anode terminal coupled to the first power supply terminal and a cathode terminal coupled to the voltage comparator, and in which a voltage drop across the diode is an absolute value of a threshold voltage V th , and in which V SP ≈V DD −|V th |.
9. The low voltage detector of claim 1 , in which V SP has complementary to absolute temperature (CTAT) behavior with respect to the voltage at the first power supply terminal, and proportional to absolute temperature (PTAT) behavior with respect to a voltage at the second power supply terminal.
10. The low voltage detector of claim 9 , in which V xm has PTAT behavior with respect to the voltage at the second power supply terminal.
11. A System-on-Chip (SoC), comprising:
a microcontroller unit (MCU), disposed on a substrate of an integrated circuit, and powered by a power supply; and
a low voltage detector, disposed on the substrate of the integrated circuit, coupled to the MCU, to a first power supply terminal of the power supply and to a second power supply terminal of the power supply, the low voltage detector including:
a voltage generator for producing a voltage V xm , related to a voltage at the second power supply terminal, the voltage generator including a single array of at least one self-cascode MOSFET (SCM) structure, in which the at least one SCM structure includes a first transistor coupled to a second transistor, wherein the second transistor is connected as a diode, and in which one SCM structure of the at least one SCM structure is coupled to the second power supply terminal of the power supply and to a current source for supplying a bias current to the first transistor and to the second transistor, the voltage generator having a temperature variation coefficient that is similar to the temperature variation coefficient of the power supply voltage monitor circuit;
a power supply voltage monitor circuit, coupled to the first power supply terminal of the power supply and coupled to a current sink, for producing a voltage V SP related to a voltage at the first power supply terminal, the power supply voltage monitor circuit having a temperature variation coefficient, and wherein the power supply voltage monitor circuit does not include an array of self-cascode MOSFET (SCM) structure; and
a voltage comparator, having a first comparator input coupled to the voltage generator for coupling the voltage V xm to the first comparator input and having a second comparator input coupled to the power supply voltage monitor circuit for coupling the voltage V SP to the second comparator input, the voltage comparator for outputting a low voltage detect output signal in response to a differential voltage between V xm and V SP , wherein the voltages V xm , and V SP have a substantially same voltage rate of change and in a same direction with respect to temperature based on the similar temperature variation coefficient of the power supply voltage monitor circuit and the voltage generator, wherein the low voltage detect output signal changes state in response to the voltage V SP being equal to the voltage V xm .
12. The SoC of claim 11 , in which V xm and V SP have proportional to absolute temperature (PTAT) behavior with respect to the second power supply terminal.
13. The SoC of claim 12 , in which the at least one SCM structure is sized to provide a rate of change with temperature of the PTAT behavior of V xm that matches a rate of change with temperature of the PTAT behavior of V SP .
14. The SoC of claim 11 , in which the power supply voltage monitor circuit includes a transistor, having a conductivity type opposite to a conductivity type of the transistors of the at least one SCM structure, connected as a diode having one current electrode coupled to the first power supply terminal and another current electrode coupled to the voltage comparator, and in which a voltage drop across the current electrodes of the transistor is a threshold voltage V th , and wherein V SP ≈V DD −|V th |.
15. The SoC of claim 14 , in which the at least one SCM structure is sized to provide a rate of change with temperature of V xm that matches a rate of change with temperature of the threshold voltage V th of the transistor of the power supply voltage monitor circuit over corner process.
16. An integrated circuit, comprising:
a voltage level detector, the voltage level detector including:
a power supply voltage monitor circuit, coupled to a current sink and including a terminal for coupling to a first power supply terminal of a power supply, the power supply voltage monitor circuit having a temperature variation coefficient, for producing a voltage V SP related to a voltage at the first power supply terminal, wherein V SP has complementary to absolute temperature (CTAT) behavior with respect to the voltage at the first power supply terminal and proportional to absolute temperature (PTAT) behavior with respect to a voltage at a second power supply terminal of the power supply;
a proportional to absolute temperature (PTAT) voltage generator, coupled to a current source and including a terminal for coupling to a second power supply terminal of the power supply, the PTAT voltage generator having a temperature variation coefficient that is similar to the temperature variation coefficient of the power supply voltage monitor circuit, for producing a voltage V xm related to the voltage at the second power supply terminal, wherein the PTAT voltage generator includes a single array of at least one self-cascode MOSFET (SCM) structure that produces the voltage V xm , wherein V xm has PTAT behavior with respect to the voltage at the second power supply terminal; and
a voltage comparator, having a first comparator input coupled to the PTAT voltage generator for coupling the voltage V xm to the first comparator input and having a second comparator input coupled to the power supply voltage monitor circuit for coupling the voltage V SP to the second comparator input, the voltage comparator for outputting a voltage level detect output signal in response to a differential voltage between V xm and V SP , wherein the voltages V xm and V SP have a substantially same voltage rate of change and in a same direction with respect to temperature based on the similar temperature variation coefficient of the power supply voltage monitor circuit and the PTAT voltage generator, and wherein the voltage level detect output signal changes state in response to the voltage V SP being equal to the voltage V xm .
17. The integrated circuit of claim 16 , in which the power supply voltage monitor circuit includes a transistor, having a conductivity type opposite to a conductivity type of the transistors of the at least one SCM structure, the transistor having a first current electrode coupled to the first power supply terminal, having a second current electrode coupled to the voltage comparator, and having a control electrode coupled to the second current electrode and to a current sink, the current sink for providing a bias current for the transistor, and in which V SP is a voltage at the second current electrode.
18. The integrated circuit of claim 17 , in which the transistor of the power supply voltage monitor circuit operates in a saturation region and in moderate inversion.
19. The integrated circuit of claim 16 , in which each of the at least one SCM structure includes a first NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor of one SCM structure of the at least one SCM structure has its source terminal coupled to a second power supply terminal, its drain terminal connected to a source terminal of the second NMOS transistor, and its gate terminal connected to a gate terminal of the second NMOS transistor, wherein the gate and drain terminals of the second NMOS transistor are connected together and coupled to a current source, and wherein the drain terminal of the first NMOS transistor is coupled to another current source.
20. The low voltage detector of claim 1 , wherein V SP is equal to a threshold voltage V th subtracted from the voltage at the first power supply terminal, and wherein V xm and V th have a substantially same voltage rate of change in opposite directions with respect to temperature.