Semiconductor devices with enclosed void cavities
View Patent ↗Field effect devices and ICs with very low gate-drain capacitance Cgd are provided by forming a substantially empty void between the gate and the drain regions. For vertical FETS a cavity is etched in the semiconductor (SC) and provided with a gate dielectric liner. A poly-SC gate deposited in the cavity has a central fissure (empty pipe) extending through to the underlying SC. This fissure is used to etch the void in the SC beneath the poly-gate. The fissure is then closed by a dielectric plug formed by deposition or oxidation without significantly filling the etched void. Conventional process steps are used to provide the source and body regions around the cavity containing the gate, and to provide a drift space and drain region below the body region. The etched void between the gate and drain provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics.
1. A semiconductor device, comprising:
a semiconductor substrate;
a first cavity formed in the substrate, the first cavity having a sidewall and a bottom;
a dielectric lining the sidewall and the bottom of the first cavity, wherein the dielectric is adapted to act as a gate insulator, wherein the gate insulator has a uniform thickness along all portions of the sidewall between an upper extent and a lower extent of a gate conductor;
the gate conductor within the cavity extending to the gate insulator at the bottom of the first cavity;
a body region of a first conductivity type located in the semiconductor substrate laterally outside the gate insulator;
a source region of a second, opposite conductivity type, in the substrate proximate an upper portion of the first cavity and the body region, adapted to inject carriers into the body region in response to a bias applied to the gate conductor;
a drain region of the second conductivity type in the substrate, coupled to the body region and adapted to collect carriers from the body region in response to a bias applied to the drain region;
a void cavity in the substrate proximate the bottom of the first cavity, located between the drain region and the gate conductor; and
a drift space of the second conductivity type underlying an entirety of the void cavity and located between the void cavity and the drain region.
2. The device of claim 1 , wherein the void cavity is located at least partially within the drift space between the gate conductor and the drain region.
3. The device of claim 1 , wherein the device is made by a process comprising forming the void cavity by etching a space within the substrate beneath the first cavity.
4. The device of claim 1 , wherein the device is made by a process comprising forming the void cavity by differential etching through a fissure in the gate conductor using reagents that attack the substrate beneath the first cavity but do not substantially attack material on a sidewall of the fissure.
5. A semiconductor device comprising:
a semiconductor substrate;
a first cavity in the semiconductor substrate, wherein the first cavity has a sidewall and a bottom;
a dielectric liner on the sidewall and the bottom of the first cavity, wherein the dielectric liner has a uniform thickness along all portions of the sidewall between an upper extent and a lower extent of a conductor;
the conductor within the cavity extending to the dielectric liner at the bottom of the first cavity;
a substantially empty void cavity in the semiconductor substrate beneath the dielectric liner;
a drain region of a first conductivity type and a first doping density underlying the void cavity; and
a drift space of the first conductivity type and a second doping density that is less than the first doping density underlying an entirety of the void cavity and located between the void cavity and the drain region.
6. The device of claim 5 , further comprising:
a fissure in the conductor, which extends to the substrate beneath the first cavity; and
a dielectric plug within the fissure.
7. The device of claim 5 , wherein the conductor is poly-silicon.
8. The device of claim 5 , wherein the dielectric liner is adapted to act as a gate insulator, and the conductor is adapted to act as a gate conductor, and the device further comprises:
a body region of a second, opposite conductivity type located in the semiconductor substrate laterally outside the gate insulator; and
a source region of the first conductivity type, in the substrate proximate an upper portion of the first cavity and the body region, adapted to inject carriers into the body region in response to a bias applied to the gate conductor,
wherein the drain region is coupled to the body region and adapted to collect carriers from the body region in response to a bias applied to the drain region, wherein the void cavity is located between the drain region and the gate conductor.
9. The device of claim 8 , wherein the void cavity is located at least partially within the drift space between the gate conductor and the drain region.
10. A semiconductor device comprising:
a semiconductor substrate;
a first cavity in the semiconductor substrate, wherein the first cavity has an interior surface;
a dielectric liner on the interior surface of the first cavity, wherein the dielectric liner has a uniform thickness along all portions of the sidewall between an upper extent and a lower extent of a conductor;
the conductor in the first cavity on the dielectric liner;
a fissure in the conductor, which extends to the semiconductor substrate;
a substantially empty void cavity in the semiconductor substrate beneath the fissure;
a drain region of a first conductivity type and a first doping density underlying the void cavity; and
a drift space of the first conductivity type and a second doping density that is less than the first doping density underlying an entirety of the void cavity and located between the void cavity and the drain region.
11. The device of claim 10 , further comprising:
a dielectric plug within the fissure.
12. The device of claim 10 , wherein the conductor is poly-silicon.
13. The device of claim 10 , wherein the dielectric liner is adapted to act as a gate insulator, and the conductor is adapted to act as a gate conductor, and the device further comprises:
a body region of a second, opposite conductivity type located in the semiconductor substrate laterally outside the gate insulator; and
a source region of the first conductivity type, in the substrate proximate an upper portion of the first cavity and the body region, adapted to inject carriers into the body region in response to a bias applied to the gate conductor,
wherein the drain region is coupled to the body region and adapted to collect carriers from the body region in response to a bias applied to the drain region, wherein the void cavity is located between the drain region and the gate conductor.
14. The device of claim 13 , wherein the void cavity is located at least partially within the drift space between the gate conductor and the drain region.
15. The device of claim 1 , wherein the first cavity extends through the body region and into but not entirely through the drift space.
16. The device of claim 15 , wherein the void cavity extends into but not entirely through the drift space so that a portion of semiconductor material forming the drift space is present between a bottom of the void cavity and the drain region.