IP Library Granted Patent US 8,447,897
Granted Patent B2
US 8,447,897 · App. 13/168,331 · Granted May 21, 2013

Bandwidth control for a direct memory access unit within a data processing system

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,447,897
App. No.
13/168,331
Granted
May 21, 2013
Kind
B2
Abstract

A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source timer; and issuing a request to read a next section of data for the DMA job. If a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job.

Claims (112)

1. A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising:

assigning a DMA job to a selected DMA engine;

starting a source timer;

issuing a request to read a next section of data for the DMA job; and

if a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job.

2. The method of claim 1 further comprising:

resetting the source timer before continuing to read the additional data; and

when either the sufficient amount of the data is obtained or all the data for the DMA job has been read, issuing a request to write a next section of data to a destination.

3. The method of claim 1 , further comprising:

starting a destination timer for the current destination;

issuing a request to write a next section of data to a destination;

if all previously read data has not been consumed by the destination and the destination timer has not reached a specified value:

allowing the DMA engine to wait until the destination timer reaches a specified value before continuing to write additional data for the DMA job.

4. The method of claim 1 , further comprising:

receiving a frame descriptor for the DMA job;

extracting attributes from the frame descriptor; and

using a source throttle control indicator in the frame descriptor or in a source descriptor for the DMA job to control the allowing the one of the DMA engines to wait until the source timer reaches the specified value before continuing to read additional data for the DMA job.

5. The method of claim 3 , further comprising:

using a destination throttle control indicator in a destination descriptor for the DMA job to control the allowing the DMA engine to wait until the destination timer reaches a specified value before continuing to write additional data for the DMA job.

6. The method of claim 1 , further comprising:

starting a destination timer;

issuing a request to write a next section of data for the DMA job to a current destination;

if all previously read data has not been consumed by the current destination before the destination timer reached a specified value:

resetting the destination timer for the current destination; and

issuing a request to write another next section of data to the current destination.

7. The method of claim 1 , further comprising:

if all previously read data has been consumed by a current destination and a total amount of data for the job has not been written to the current destination:

when there is another destination that has not consumed current data:

storing a state of the current destination to a breakpoint buffer,

selecting the other destination as the current destination,

resetting a destination timer for the current destination, and

starting the destination timer for the current destination and issuing a request to write a next section of data to the current destination.

8. A method for operating a direct memory access (DMA) unit, the method comprising:

receiving a destination descriptor for a DMA job;

extracting attributes including a destination throttle control indicator from the destination descriptor;

issuing a request to read a section of data for the DMA job;

issuing a request to write the section of data to a current destination;

starting a destination timer for the current destination;

if the DMA job is not complete and a destination timer has not reached a specified value based on the destination throttle control indicator:

allowing the DMA engine to wait until the destination timer reaches a specified value before continuing to write additional data for the current job.

9. The method of claim 8 further comprising:

receiving a frame descriptor for the DMA job;

assigning the DMA job to a selected DMA engine;

extracting a source throttle control indicator from the frame descriptor;

starting a source timer;

issuing a request to read a next section of data for the DMA job; and

if a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value based on the source throttle indicator before continuing to read additional data for the DMA job.

10. The method of claim 8 , further comprising:

if a sufficient amount of the data was obtained, selecting a current destination of the DMA job;

restoring a state of the current destination from a breakpoint buffer, if the state is available;

when the destination timer the current destination has exceeded a specified limit:

resetting the destination timer for the current destination, and

starting the destination timer for the current destination, and issuing a request to write at least a portion of the data to the current destination.

11. The method of claim 8 , further comprising:

if all previously read data has been consumed by the current destination and a total amount of data for the DMA job has been written to the current destination:

when there is an incomplete destination for the job:

selecting the incomplete destination as the current destination for the DMA job,

restoring a state of the current destination from a breakpoint buffer, if the state is available,

when the destination timer for the current destination has exceeded a specified limit:

resetting a destination timer for the current destination,

starting the destination timer for the current destination, and issuing a request to write at least a portion of the data to the current destination;

if all previously read data has been consumed by the current destination and a total amount of data for the DMA job has not been written to the current destination:

when there is another destination that has not consumed current data:

storing a state of the current destination to a breakpoint buffer,

selecting the other destination as the current destination,

resetting a destination timer for the current destination, and

starting the destination timer for the current destination and issuing a request to write the next section of data to the current destination.

12. A computer processing system comprising:

a direct memory access (DMA) unit that includes:

a DMA engine operable to control a rate at which data is read from a source address and a rate at which the data is written to a destination for a DMA job, wherein

the DMA engine receives a source throttle control indicator for the DMA job that is set to indicate to the DMA engine to wait if a next section of the data has been read within a specified amount of time and continue reading the data at a later time.

13. The system of claim 12 wherein:

when the source throttle control indicator is set and a sufficient amount of the data has been read or all the data for the DMA job has been read, the DMA engine issues a request to write a section of the data to a destination.

14. The system of claim 12 wherein:

when the source throttle control indicator is set:

the DMA engine maintains a source timer; and

when a sufficient amount of the data has not been read, all the data for the DMA job has not been read, and the source timer is less than a specified value, the DMA engine waits until the source timer reaches the specified value, resets the timer, starts the timer and issues a request to read a next data section from the source address.

15. The system of claim 12 , wherein

the DMA engine receives a write throttle control indicator for the DMA job that is set to indicate to the DMA engine to store a state of the current destination and select a next incomplete destination as the current destination when either:

all previously read data has been consumed by the current destination, all of the data for the DMA job has not been written to the current destination, and there is another destination that has not consumed all of the previously read data; or

all previously read data has not been consumed by the current destination and a destination timer for the current destination has not exceeded a specified limit.

16. The system of claim 15 wherein:

when all previously read data has not been consumed by the current destination and the destination timer has exceeded the specified time limit, the DMA engine

resets the destination timer for the current destination,

starts the destination timer for the current destination, and

issues a request to write a next section of the data to the current destination.

17. The system of claim 12 further comprising:

a plurality of DMA engines, wherein the DMA engines process a corresponding one of a plurality of DMA jobs; and

a breakpoint buffer coupled to the DMA engines, wherein the breakpoint buffer stores information regarding status of writing the data for the DMA jobs.

18. The system of claim 12 , wherein

if the DMA engine determines that all previously read data has been consumed by the current destination and a total amount of data for the DMA job has been written to the current destination:

when there is an incomplete destination for the job, the DMA engine:

selects the incomplete destination as the current destination for the DMA job,

restores a state of the current destination from a breakpoint buffer, if the state is available,

when the destination timer for the current destination has exceeded a specified limit:

resets a destination timer for the current destination,

starts the destination timer for the current destination, and issues a request to write at least a portion of the data to the current destination.

19. The system of claim 12 , wherein

when the destination timer for the current destination has not exceeded a specified limit and when there is an incomplete destination for the job:

selects a next incomplete destination as the current destination for the DMA job,

restores a state of the current destination from a breakpoint buffer, if the state is available, and

when the destination timer the current destination has exceeded a specified limit:

resets a destination timer for the current destination, and

starts the destination timer for the current destination, and issues a request to write at least a portion of the data to the current destination.

20. The system of claim 12 , wherein

if the DMA engine determines that all previously read data has been consumed by

the current destination and a total amount of data for the DMA job has not been written to the current destination:

when there is another destination that has not consumed current data, the DMA engine:

stores a state of the current destination to a breakpoint buffer,

selects the other destination as the current destination,

resets a destination timer for the current destination, and

starts the destination timer for the current destination and issues a request to write the next section of data to the current destination.

Assignments (18)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2025
From: NXP USA, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 072889/0939 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →