Differential equalizers with source degeneration and feedback circuits
View Patent ↗An embodiment of an equalizer includes a voltage-to-current converter and a current-to-voltage converter. The voltage-to-current converter is configured to convert a differential input voltage to a differential current, and includes a differential amplifier with a first transistor and a second transistor, and a first source degeneration circuit coupled between the first transistor and the second transistor. An embodiment of the first source degeneration circuit includes a first resonant circuit. The current-to-voltage converter is coupled to the voltage-to-current converter, and is configured to convert the differential current to a differential output voltage. The current-to-voltage converter includes a first inverter with a first feedback circuit and a second inverter coupled to the first inverter, which includes a second feedback circuit. An embodiment of the first feedback circuit includes a second resonant circuit, and an embodiment of the second feedback circuit includes a third resonant circuit.
1. An equalizer comprising:
a voltage-to-current converter configured to convert a differential input voltage to a differential current, the voltage-to-current converter comprising:
a differential amplifier having a first transistor and a second transistor, and
a first source degeneration circuit coupled between the first transistor and the second transistor, wherein the first source degeneration circuit includes a first resonant circuit; and
a current-to-voltage converter coupled to the voltage-to-current converter, wherein the current-to-voltage converter is configured to convert the differential current to a differential output voltage, the current-to-voltage converter comprising:
a first inverter with a first feedback circuit, wherein the first feedback circuit includes a second resonant circuit, and
a second inverter coupled to the first inverter, wherein the second inverter includes a second feedback circuit having a third resonant circuit.
2. The equalizer of claim 1 , wherein the first source degeneration circuit comprises:
a resistor circuit coupled in parallel with the first resonant circuit,
wherein the first resonant circuit comprises a capacitor circuit coupled in series with an inductor circuit.
3. The equalizer of claim 2 , wherein the resistor circuit comprises a variable resistor circuit.
4. The equalizer of claim 2 , wherein the capacitor circuit comprises a variable capacitor circuit.
5. The equalizer of claim 1 , wherein the first transistor is a field effect transistor (FET) with a first source, a first gate, and a first drain, and the second transistor is a FET with a second source, a second gate, and a second drain, and the first source degeneration circuit is coupled between the first source and the second source.
6. The equalizer of claim 1 , wherein:
the first feedback circuit comprises
a first resistor circuit coupled in series with the second resonant circuit,
wherein the second resonant circuit comprises a first capacitor circuit coupled in parallel with a first inductor circuit; and
the second feedback circuit comprises
a second resistor circuit coupled in series with the third resonant circuit,
wherein the third resonant circuit comprises a second capacitor circuit coupled in parallel with a second inductor circuit.
7. The equalizer of claim 6 , wherein the first resistor circuit comprises a first variable resistor circuit, and the second resistor circuit comprises a second variable resistor circuit.
8. The equalizer of claim 6 , wherein the first capacitor circuit comprises a first variable capacitor circuit, and the second capacitor circuit comprises a second variable capacitor circuit.
9. The equalizer of claim 1 , wherein the voltage-to-current converter and the current-to-voltage converter form portions of a primary equalizer, and the equalizer further comprises:
a secondary equalizer coupled in series with the primary equalizer, wherein the secondary equalizer comprises an additional voltage-to-current converter coupled in series with an additional current-to-voltage converter; and
control circuitry configured to determine whether an over-equalization condition or an under-equalization condition is present, wherein the control circuitry is further configured to cause the secondary equalizer to function as a limiter circuit when the over-equalization condition is present and to cause the secondary equalizer to function as an extended equalizer stage when the under-equalization condition is present.
10. The equalizer of claim 1 , wherein the voltage-to-current converter further comprises a pair of current sources.
11. The equalizer of claim 1 , wherein the voltage-to-current converter further comprises a current mirror circuit.
12. The equalizer of claim 1 , wherein the current-to-voltage converter further comprises a current sink coupled to the first inverter and the second inverter.
13. The equalizer of claim 12 , wherein:
the first inverter comprises a first field effect transistor (FET) having a first source, a first gate, and a first drain, and a second FET having a second source, a second gate, and a second drain, wherein the first source and the second source are coupled together, to an inverting output, and to the first feedback circuit;
the second inverter comprises a third FET having a third source, a third gate, and a third drain, and a fourth FET having a fourth source, a fourth gate, and a fourth drain, wherein the third source and the fourth source are coupled together, to a non-inverting output, and to the second feedback circuit; and
wherein the current sink is coupled to the second drain of the first inverter and to the fourth drain of the second inverter.
14. An equalizer comprising:
a voltage-to-current converter configured to convert a differential input voltage to a differential current, the voltage-to-current converter comprising:
a differential amplifier having a first transistor and a second transistor, and
a first source degeneration circuit coupled between the first transistor and the second transistor, wherein the first source degeneration circuit includes a first resonant circuit; and
a current-to-voltage converter coupled to the voltage-to-current converter, wherein the current-to-voltage converter is configured to convert the differential current to a differential output voltage, the current-to-voltage converter comprising
a first inverter, and
a second inverter coupled to the first inverter.
15. The equalizer of claim 14 , wherein the first source degeneration circuit comprises:
a resistor circuit coupled in parallel with the first resonant circuit,
wherein the first resonant circuit comprises a capacitor circuit coupled in series with an inductor circuit.
16. The equalizer of claim 14 , wherein:
the first inverter includes a first feedback circuit with a second resonant circuit; and
the second inverter includes a second feedback circuit with a third resonant circuit.
17. The equalizer of claim 14 , wherein the current-to-voltage converter further comprises a current sink coupled to the first inverter and the second inverter.
18. The equalizer of claim 14 , wherein the voltage-to-current converter and the current-to-voltage converter form portions of a primary equalizer, and the equalizer further comprises:
a secondary equalizer coupled in series with the primary equalizer, wherein the secondary equalizer comprises an additional voltage-to-current converter coupled in series with an additional current-to-voltage converter; and
control circuitry configured to determine whether an over-equalization condition or an under-equalization condition is present, wherein the control circuitry is further configured to cause the secondary equalizer to function as a limiter circuit when the over-equalization condition is present and to cause the secondary equalizer to function as an extended equalizer stage when the under-equalization condition is present.
19. An equalizer comprising:
a voltage-to-current converter configured to convert a differential input voltage to a differential current, the voltage-to-current converter comprising:
a differential amplifier having a first transistor and a second transistor, and
a first source degeneration circuit coupled between the first transistor and the second transistor; and
a current-to-voltage converter coupled to the voltage-to-current converter, wherein the current-to-voltage converter is configured to convert the differential current to a differential output voltage, the current-to-voltage converter comprising
a first inverter with a first feedback circuit, wherein the first feedback circuit includes a first resonant circuit, and
a second inverter coupled to the first inverter, wherein the second inverter includes a second feedback circuit having a second resonant circuit.
20. The equalizer of claim 19 , wherein the first source degeneration circuit includes a third resonant circuit.
21. The equalizer of claim 19 , wherein:
the first feedback circuit comprises
a first resistor circuit coupled in series with the first resonant circuit,
wherein the first resonant circuit comprises a first capacitor circuit coupled in parallel with a first inductor circuit; and
the second feedback circuit comprises
a second resistor circuit coupled in series with the second resonant circuit,
wherein the second resonant circuit comprises a second capacitor circuit coupled in parallel with a second inductor circuit.
22. The equalizer of claim 19 , wherein the voltage-to-current converter and the current-to-voltage converter form portions of a primary equalizer, and the equalizer further comprises:
a secondary equalizer coupled in series with the primary equalizer, wherein the secondary equalizer comprises an additional voltage-to-current converter coupled in series with an additional current-to-voltage converter; and
control circuitry configured to determine whether an over-equalization condition or an under-equalization condition is present, wherein the control circuitry is further configured to cause the secondary equalizer to function as a limiter circuit when the over-equalization condition is present and to cause the secondary equalizer to function as an extended equalizer stage when the under-equalization condition is present.