Method and apparatus for interleaving a data stream using quadrature permutation polynomial functions (QPP)
A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.
1. A semiconductor device comprising processing logic, the processing logic being arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial (QPP) function;
wherein the processing logic is arranged to divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions;
wherein the processor logic is arranged to derive inverse functions for the set of linear functions defining the subgroups and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.
2. The semiconductor device of claim 1 wherein the interleaver logic comprises recursive interleaving logic.
3. The semiconductor device of claim 2 wherein the QPP function defines a cyclic group of values of order M, and the processing logic is arranged to divide the cyclic group of values defined by the QPP function into a set of K subgroups of order M/K.
4. The semiconductor device of claim 2 wherein the processing logic is arranged to derive inverse functions for the set of linear functions defining the subgroups by linearly transforming said linear functions defining the subgroups such that values defined by the transformed functions comprise values from 0 to ((M/K)−1), deriving inverse functions for the transformed functions, and linearly transforming said inverse functions to derive inverse functions for the set of linear functions defining the subgroups.
5. The semiconductor device of claim 1 wherein the QPP function defines a cyclic group of values of order M, and the processing logic f2-i-Gf is arranged to divide the cyclic group of values defined by the QPP function into a set of K subgroups of order M/K.
6. The semiconductor device of claim 5 wherein the each cyclic subgroup of values defined by an inverse linear function is represented by an initial value, a step value, which when added to a value within the subgroup derives the next value in the subgroup, and a modulo value.
7. The semiconductor device of claim 5 wherein the interleaver logic is arranged to perform interleaving operations within a turbo encoder.
8. The semiconductor device of claim 1 wherein the processing logic is arranged to derive inverse functions for the set of linear functions defining the subgroups by linearly transforming said linear functions defining the subgroups such that values defined by the transformed functions comprise values from 0 to ((M/K)−1), deriving inverse functions for the transformed functions; and linearly transforming said inverse functions to derive inverse functions for the set of linear functions defining the subgroups.
9. The semiconductor device of claim 1 wherein the QPP function is given by Pi(x)=(f1x+f2x2)% M, where M, f1 and f2 are parameters, sets of which are predefined.
10. The semiconductor device of claim 9 wherein the processing logic f2-i-Gf is arranged to derive the subgroups, into which the cyclic group of values defined by the OPP function is divided, by calculating recursions of:
Ri:Ri[O]= ( f 1 i+f 2 i 2)% M;Ri[x]= ( Ri[x− 1 ]+Kf 1 +K 2 f 2+2 Kif 2)% M
where: f1, f2 and M comprise parameters of the OPP function, K is a divisor factor, i is an index of a recursive element comprising the range i=0 to K1, and R is the recursive element.
11. The semiconductor device of any preceding claim 1 wherein the each cyclic subgroup of values defined by an inverse linear function is represented by an initial value, a step value, which when added to a value within the subgroup derives the next value in the subgroup, and a modulo value.
12. The semiconductor device of claim 11 wherein the processing logic is arranged to configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to the cyclic group of values representative of the inverse function for the QPP function by programming a plurality of initial values, step values and a modulo value into programmable elements of the interleaver logic.
13. The semiconductor device of any preceding claim 1 wherein the interleaver logic and forms an integral part of the semiconductor device.
14. The semiconductor device of claim 1 wherein the semiconductor device is adapted to be operably coupled to the interleaver logic discrete from the semiconductor device.
15. The semiconductor device of any preceding claim 1 wherein the interleaver logic is arranged to perform interleaving operations within a turbo encoder.
16. The semiconductor device of claim 15 wherein the interleaver logic is arranged to perform interleaving operations within a transceiver for a mobile communication device.
17. The semiconductor device of claim 1 wherein the interleaver logic is arranged to perform interleaving operations within a turbo decoder.
18. A method for interleaving a data stream according to a quadrature permutation polynomial (QPP) function, wherein the method comprises:
dividing, by processing logic of a semiconductor device, a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions;
deriving, by the processing logic, inverse functions for the set of linear functions defining the subgroups; and
loading data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.
19. A non-transitory computer-readable storage element having computer-readable code stored thereon for programming signal processing logic to perform-interleaving a data stream according to a quadrature permutation polynomial (QPP) function, wherein the signal processing logic when programmed with the code perform the method comprising the code
dividing a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions;
deriving inverse functions for the set of linear functions defining the subgroups; and
loading data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.
20. The computer-readable storage element of claim 19 , wherein the computer readable storage medium comprises at least one of a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a ROM (Read Only Memory), a PROM (Programmable Read Only Memory), a EPROM (Erasable Programmable Read Only Memory), a EEPROM (Electrically Erasable Programmable Read Only Memory) and a Flash memory.