Patterning a gate stack of a non-volatile memory (NVM) using a dummy gate stack
View Patent ↗A dummy gate stack is created in an area different from a region where the non-volatile memory (NVM) array is located. The dummy gate stack is used to simulate an actual NVM gate stack used in the NVM array. During an etch of the NVM gate stack, the dummy gate stack is also etched so that the end of both the stack etches occur at the same time. This allows for improved end point detection of the NVM gate stack etch due to increased endpoint material being exposed at the end of the etch. Also other tiling features may be formed during the etch of the dummy gate stack.
1. A method for forming a gate stack of a non-volatile memory (NVM) over a semiconductor substrate having an NVM region and a non-NVM region which does not overlap the NVM region, the method comprising:
forming an isolation region in the non-NVM region;
forming a dummy dielectric in an area of the non-NVM region surrounded by the isolation region and forming a gate dielectric in the NVM region;
after forming the dummy dielectric and the gate dielectric, forming a first conductive layer over the substrate in the NVM region and the non-NVM region;
patterning the first conductive layer in the non-NVM region;
after patterning the first conductive layer, forming an NVM dielectric layer over the NVM region and the non-NVM region;
forming a second conductive layer over the NVM dielectric layer;
forming a patterned masking layer over the second conductive layer in the NVM region and in the non-NVM region, wherein:
the patterned masking layer defines at least one NVM gate stack in the NVM region and at least one dummy feature in the non-NVM region, wherein the dummy feature is over the isolation, and
performing an etch comprising:
simultaneously etching the second conductive layer in the NVM region and in the non-NVM region using the patterned masking layer;
simultaneously etching the NVM dielectric layer in the NVM region and in the non-NVM region using the patterned masking layer; and
simultaneously etching the first conductive layer in the NVM region and in the non-NVM region using the patterned masking layer,
using the dummy dielectric in endpoint detection of the etch.
2. The method of claim 1 , wherein the dummy feature is a tiling feature.
3. The method of claim 1 , wherein after performing the etch, a resulting dummy feature corresponding to the dummy feature defined by the patterned masking layer comprises a remaining portion of the NVM dielectric layer over the substrate and a remaining portion of the second conductive layer over the remaining portion of the NVM dielectric layer, wherein the resulting dummy feature does not include any remaining portion of the first conductive layer.
4. The method of claim 1 , wherein after performing the etch, the resulting dummy feature defined by the patterned masking layer comprises a remaining portion of the NVM dielectric layer.
5. A method for forming a gate stack of a non-volatile memory (NVM) over a semiconductor substrate having an NVM region and a non-NVM region which does not overlap the NVM region, the method comprising:
forming an isolation region in the non-NVM region;
forming a dummy dielectric in an area of the non-NVM region surrounded by the isolation region and forming a gate dielectric in the NVM region;
forming a first conductive layer over the substrate in the NVM region and the non-NVM region;
patterning the first conductive layer in the non-NVM region;
forming an NVM dielectric layer over the first conductive layer in the NVM region and the non-NVM region;
forming a second conductive layer over the NVM dielectric layer in the NVM region and the non-NVM region;
forming a patterned masking layer over the second conductive layer in the NVM region and in the non-NVM region, wherein the patterned masking layer defines at least one NVM gate stack in the NVM region and at least one dummy feature in the non-NVM region, wherein the patterned masking layer defines the at least one dummy feature over the isolation region in the non-NVM region;
performing an etch comprising:
simultaneously etching the second conductive layer in the NVM region and in the non-NVM region using the patterned masking layer;
simultaneously etching the NVM dielectric layer in the NVM region and in the non-NVM region using the patterned masking layer; and
simultaneously etching the first conductive layer in the NVM region and in the non-NVM region using the patterned masking layer; and
using the dummy dielectric in an endpoint detection of the etch.
6. The method of claim 5 , wherein the performing the etch results in a dummy gate stack corresponding to the at least one dummy feature that functions as a tile in a subsequent step of chemical mechanical polishing.
7. The method of claim 6 , wherein after the steps of simultaneously etching, a resulting dummy feature corresponding to the at least one dummy feature defined by the patterned masking layer comprises a remaining portion of the NVM dielectric layer over the substrate and a remaining portion of the second conductive layer over the remaining portion of the NVM dielectric layer, wherein the resulting dummy feature does not include any remaining portion of the first conductive layer.
8. The method of claim 5 , wherein after performing the etch, an NVM gate stack remains on the NVM portion.