Laterally diffused metal oxide semiconductor device
View Patent ↗A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
1. A semiconductor device comprising:
a semiconductor-on-insulator substrate comprising a support layer, a buried insulator layer overlying the support layer, and a layer of semiconductor material overlying the buried insulator layer;
additional semiconductor material overlying the layer of semiconductor material, the additional semiconductor material comprising a first semiconductor region having a first conductivity type;
a second semiconductor region located in the additional semiconductor material and having a second conductivity type;
a third semiconductor region located in the additional semiconductor material above the second semiconductor region and having the first conductivity type;
a fourth semiconductor region located in the additional semiconductor material above the third semiconductor region and having the second conductivity type;
a fifth semiconductor region located in the additional semiconductor material above the second semiconductor region and having the second conductivity type, the fifth semiconductor region being adjacent to both the third semiconductor region and the fourth semiconductor region; and
a sixth semiconductor region located in the additional semiconductor material adjacent to the fourth semiconductor region and having the first conductivity type, wherein no portion of the second semiconductor region is located under the sixth semiconductor region.
2. The semiconductor device of claim 1 , further comprising a semiconductor contact region located in the fifth semiconductor region, and having the second conductivity type.
3. The semiconductor device of claim 2 , wherein the fifth semiconductor region electrically couples the second semiconductor region and the fourth semiconductor region to the semiconductor contact region.
4. The semiconductor device of claim 1 , further comprising a semiconductor contact region located in the sixth semiconductor region and having the second conductivity type.
5. The semiconductor device of claim 1 , wherein the fourth semiconductor region separates the fifth semiconductor region from the sixth semiconductor region.
6. The semiconductor device of claim 1 , wherein no portion of the third semiconductor region is located under the sixth semiconductor region.
7. The semiconductor device of claim 1 , further comprising a gate structure that overlies a portion of the fourth semiconductor region and overlies a portion of the sixth semiconductor region.
8. The semiconductor device of claim 7 , wherein:
the fifth semiconductor region serves as a drain region of a transistor;
the sixth semiconductor region serves as a source region of the transistor; and
the gate structure serves as the gate of the transistor.
9. The semiconductor device of claim 1 , further comprising an eighth semiconductor region located in the additional semiconductor material above the buried insulator layer and below the second semiconductor region, and having the first conductivity type.
10. The semiconductor device of claim 1 , wherein:
the fifth semiconductor region is more heavily doped than any of the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; and
the additional semiconductor material is more lightly doped than any of the second semiconductor region, the third semiconductor region, and the fourth semiconductor region.
11. A semiconductor device formed on a support substrate, the semiconductor device comprising:
a buried oxide layer overlying the support substrate;
a first semiconductor region located above the buried oxide layer and having a first conductivity type;
a second semiconductor region located above the first semiconductor region and having a second conductivity type;
a third semiconductor region located above the second semiconductor region and having the first conductivity type;
a fourth semiconductor region located above the third semiconductor region and having the second conductivity type;
a fifth semiconductor region extending through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and having the second conductivity type; and
a sixth semiconductor region located in the additional semiconductor material adjacent to the fourth semiconductor region and having the first conductivity type, wherein no portion of the second semiconductor region is located under the sixth semiconductor region.
12. The semiconductor device of claim 11 , further comprising epitaxially grown semiconductor material located above the buried oxide layer, wherein:
the first semiconductor region comprises a portion of the epitaxially grown semiconductor material; and
the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are all located in the epitaxially grown semiconductor material.
13. The semiconductor device of claim 11 , further comprising a semiconductor contact region located in the fifth semiconductor region and having the second conductivity type, wherein the fifth semiconductor region electrically couples the second semiconductor region to the semiconductor contact region.
14. The semiconductor device of claim 11 , further comprising:
a layer of semiconductor material overlying the buried oxide layer; and
epitaxially grown semiconductor material overlying the layer of semiconductor material; wherein:
the first semiconductor region comprises a portion of the epitaxially grown semiconductor material; and
the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are all located in the epitaxially grown semiconductor material.
15. A semiconductor device comprising:
a semiconductor-on-insulator substrate comprising a support layer, a buried insulator layer overlying the support layer, and a layer of semiconductor material overlying the buried insulator layer;
additional semiconductor material overlying the layer of semiconductor material, the additional semiconductor material comprising a first semiconductor region having a first conductivity type;
a second semiconductor region located in the additional semiconductor material and having a second conductivity type;
a third semiconductor region located in the additional semiconductor material above the second semiconductor region and having the first conductivity type;
a fourth semiconductor region located in the additional semiconductor material above the third semiconductor region and having the second conductivity type;
a fifth semiconductor region located in the additional semiconductor material above the second semiconductor region and having the second conductivity type, the fifth semiconductor region being adjacent to both the third semiconductor region and the fourth semiconductor region, wherein the fifth semiconductor region electrically couples the second semiconductor region and the fourth semiconductor region to a semiconductor contact region; and
a sixth semiconductor region located in the additional semiconductor material adjacent to the fourth semiconductor region and having the first conductivity type; wherein:
no portion of the second semiconductor region is located under the sixth semiconductor region;
no portion of the third semiconductor region is located under the sixth semiconductor region; and
the fourth semiconductor region separates the fifth semiconductor region from the sixth semiconductor region.