Exponential charge pump
View Patent ↗An exponential multistage charge pump is provided wherein node voltages in a pumpcell in one stage of the charge pump are used to control operation of clock drivers in a subsequent stage of the charge pump.
1. A method of using a charge pump comprising:
providing an input voltage to an input terminal of a first pumpcell, of a first stage of said charge pump;
using said first pumpcell to generate a first stage output voltage from said input voltage and to generate therefrom a first stage node voltage at a junction of a first transistor pair in said first pumpcell;
providing said first stage output voltage to an input terminal of a first clock driver transistor in a second stage of said charge pump; and
using said first stage node voltage to control operation of said first clock driver transistor to control generation of a second stage output voltage from said second stage of said charge pump, where said charge pump is a hybrid charge pump comprising a plurality of stages in an exponential configuration and a plurality of stages in an arithmetic configuration.
2. The method of claim 1 , further comprising:
using a second pumpcell of said second stage of said charge pump to generate said second stage output voltage and a second stage node voltage at a junction of a second transistor pair in said second pumpcell;
providing said second stage output voltage to an input terminal of a clock driver transistor in a third stage of said charge pump; and
using said second stage node voltage to control operation of said clock driver transistor in said third stage of said charge pump.
3. The method of claim 1 , wherein said plurality of stages in the exponential configuration comprises a plurality of stacked stages.
4. The method of claim 1 ,
wherein the first transistor pair in said first pumpcell comprises a pMOS/nMOS transistor pair having respective current terminals coupled together to provide said junction.
5. The method of claim 1 , wherein said first pumpcell further comprises a second transistor pair and wherein said first and second transistor pairs are cross-coupled.
6. The method of claim 1 , wherein said second stage comprises a clock driver comprising said first clock driver transistor and a second clock driver transistor.
7. The method of claim 6 , wherein operation of said first clock driver transistor is controlled by said first stage node voltage and said second clock driver transistor is controlled by a clock signal.
8. The method of claim 7 , wherein said first clock driver transistor comprises a pMOS transistor and said second clock driver transistor comprises an nMOS transistor.
9. The method of claim 7 , wherein said clock signal is further used to control operation of a clock driver transistor in the first stage of said charge pump.
10. A charge pump, comprising:
a first stage pumpcell, of a first stage of the charge pump, comprising first and second inverters coupled to receive an input voltage and to generate a first stage output voltage therefrom;
first and second capacitors, each having first and second terminals, said first terminals of said first and second capacitors being coupled to first and second nodes, respectively, of said first and second inverters;
first and second clock drivers coupled to said second terminals of said first and second capacitors, respectively, wherein said first and second clock drivers are responsive to first and second clock signals to control charging of said first and second capacitors, respectively, thereby generating first and second node voltages at said first and second nodes; and
wherein said first and second node voltages are used to control operation of third and fourth clock drivers in a second stage of said charge pump, and wherein said charge pump is a hybrid charge pump comprising a plurality of stages in an exponential configuration and a plurality of stages in an arithmetic configuration.
11. The charge pump of claim 10 , further comprising:
third and fourth inverters in said second stage pumpcell coupled to receive said first stage output voltage and to generate a second stage output voltage therefrom;
third and fourth capacitors, each having first and second terminals, said first terminals of said third and fourth capacitors being coupled to third and fourth nodes, respectively, of said third and fourth inverters in said second stage pumpcell;
wherein said third and fourth clock drivers are coupled to said second terminals of said third and fourth capacitors, respectively, and said third and fourth clock drivers are responsive to said first and second clock signals, respectively, and to said first and second node voltages, respectively, of said first stage pumpcell to control charging of said third and fourth capacitors, respectively, thereby generating third and fourth node voltages at said third and fourth nodes.
12. The charge pump of claim 11 , wherein said third and fourth node voltages are used to control operation of fifth and sixth clock drivers in a third stage of said charge pump.
13. The charge pump of claim 10 , wherein said plurality of stages in the exponential configuration comprises a plurality of stacked stages.
14. The charge pump of claim 11 , wherein said first and second inverters are cross-coupled and said third and fourth inverters are cross-coupled.
15. The charge pump of claim 12 , wherein said fifth and sixth clock drivers each comprise a pMOS/nMOS transistor pair and said third and fourth node voltages are provided to the control gates of the respective pMOS transistors in said fifth and sixth clock drivers.
16. The charge pump of claim 15 , wherein the control gates of the respective nMOS transistors are controlled by said first and second clock signals, respectively, and wherein the voltage amplitudes of said third and fourth node voltages are higher than the voltage amplitudes of said first and second clock signals.
17. The charge pump of claim 10 , wherein said third and fourth clock drivers each comprise a pMOS/nMOS transistor pair and said first and second node voltages are provided to the control gates of the respective pMOS transistors in said third and fourth clock drivers.
18. The charge pump of claim 17 , wherein the control gates of the respective nMOS transistors are controlled by said first and second clock signals, respectively, and wherein the voltage amplitudes of said first and second node voltages are higher than the voltage amplitudes of said first and second clock signals.