IP Library Granted Patent US 8,791,582
Granted Patent B2
US 8,791,582 · App. 12/844,922 · Granted Jul 29, 2014

Integrated circuit package with voltage distributor

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Quick Facts
Patent No.
US 8,791,582
App. No.
12/844,922
Granted
Jul 29, 2014
Kind
B2
Abstract

An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

Claims (89)

1. An integrated circuit package, comprising:

a package support;

a semiconductor die attached to the package support, wherein the semiconductor die has a plurality of peripheral bond pads along a periphery of the semiconductor die and a first bond pad on an interior portion of the semiconductor die, wherein the first bond pad is a bond pad for a first power supply voltage domain of the semiconductor die;

a conductive distributor over the semiconductor die, wherein:

the conductive distributor is within a perimeter of the semiconductor die;

the plurality of peripheral bond pads are located between the perimeter of the semiconductor die and a perimeter of the conductive distributor;

the conductive distributor has a first opening, and

the first bond pad is in the first opening;

a first bond wire connected to the first bond pad and the conductive distributor; and

a second bond wire connected to a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

2. The integrated circuit package of claim 1 , further comprising:

a third bond wire and a fourth bond wire;

wherein:

the conductive distributor has a first conductive layer, a second conductive layer over the first conductive layer and recessed from the first conductive layer, and an insulator separating the first conductive layer and the second conductive layer;

the semiconductor die further comprises a second bond pad in the first opening, wherein the second bond pad is a bond pad for a second power supply voltage domain of the semiconductor die;

the first bond wire is connected to the first conductive layer;

the second bond wire is connected to the first conductive layer;

the third bond wire is connected between the second conductive layer and the second bond pad; and

the fourth bond wire is connected between the second conductive layer and a second peripheral bond pad of the plurality of peripheral bond pads.

3. The integrated circuit package of claim 2 , wherein the first power supply voltage domain is a positive power supply voltage and the second power supply voltage domain is ground.

4. The integrated circuit package of claim 2 , wherein:

the conductive distributor has a second opening;

the semiconductor die further comprises a third bond pad in the second opening, wherein the third bond pad is a bond pad for the first power supply voltage domain;

the semiconductor die further comprises a fourth bond pad in the second opening, wherein the fourth bond pad is a bond pad for the second power supply voltage domain; and

the integrated circuit package further comprises:

a fifth bond wire connected to the first conductive layer and the third bond pad; and

a sixth bond wire connected to the second conductive layer and the fourth bond pad.

5. The integrated circuit package of claim 2 , wherein:

the semiconductor die further comprises a third bond pad in the first opening, wherein the third bond pad is a bond pad for the first power supply voltage domain;

the semiconductor die further comprises a fourth bond pad in the first opening, wherein the fourth bond pad is a bond pad for the second power supply voltage domain; and

the integrated circuit package further comprises:

a fifth bond wire connected to the first conductive layer and the third bond pad; and

a sixth bond wire connected to the second conductive layer and the fourth bond pad.

6. The integrated circuit package of claim 1 , further comprising:

a third bond wire;

wherein:

the semiconductor die further comprises a second bond pad in the first opening, wherein the second bond pad is a bond pad for the first power supply voltage domain; and

the third bond wire is connected between the second bond pad and the conductive distributor.

7. The integrated circuit package of claim 1 , further comprising a third bond wire connected between a second peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

8. The integrated circuit package of claim 1 , further comprising:

a third bond wire;

wherein:

the conductive distributor has a second opening;

the semiconductor die further comprises a second bond pad in the second opening; and

the third bond wire is connected between the conductive distributor and the second bond pad.

9. The integrated circuit package of claim 1 wherein:

the conductive distributor is an interleaved distributor and includes a first conductive structure of the first power supply voltage domain and a second conductive structure of a second power supply voltage domain of the semiconductor die;

the first bond wire and the second bond wire are connected to the first conductive structure;

the integrated circuit package includes a third bond wire and a fourth bond wire;

the interleaved distributor has a second opening;

the semiconductor die further comprises a second bond pad in the second opening in the interleaved distributor;

the third bond wire is connected between the second conductive structure of the second power supply voltage domain and the second bond pad; and

the fourth bond wire is connected between the second conductive structure of the second power supply voltage domain and a second peripheral bond pad of the plurality of peripheral bond pads.

10. The integrated circuit package of claim 1 wherein:

the package support includes a plurality of wire bonding surfaces;

no bond wire of the integrated circuit package is connected to both a wire bonding surface of the package support and the conductive distributor.

11. The integrated circuit package of claim 1 further comprising:

a third bond wire, the third bond wire connected to the first peripheral bond pad and a wire bonding surface of the package support.

12. The integrated circuit package of claim 1 wherein the conductive distributor includes an outer portion, a center portion, and a plurality of arms connecting the outer portion to the center portion, wherein the first opening is defined by the outer portion, the center portion and two arms of the plurality of arms.

13. The integrated circuit package of claim 1 wherein the conductive distributor includes a center portion having a continuous surface area, the continuous surface area is large enough to contain a geometric circle having a diameter in the range of 1 to 1.5 millimeters.

14. An integrated circuit package, comprising:

a package support;

a semiconductor die attached to the package support, wherein the semiconductor die has a plurality of peripheral bond pads along a periphery of the semiconductor die and a first bond pad on an interior portion of the semiconductor die, wherein the first bond pad is a bond pad for a first power supply voltage domain of the semiconductor die;

a first conductive distributor over a first portion of the semiconductor die and contained within a perimeter of the semiconductor die,

a first bond wire connected to the first bond pad and the first conductive distributor; and

a second bond wire connected to a first peripheral bond pad of the plurality of peripheral bond pads and the first conductive distributor;

a third bond wire, the third bond wire connected to the first peripheral bond pad;

a wire bonding surface of the package support, wherein the third bond wire is connected to the wire bonding surface.

15. An integrated circuit package, comprising:

a package support;

a semiconductor die attached to the package support, wherein the semiconductor die has a plurality of peripheral bond pads along a periphery of the semiconductor die and a first bond pad on an interior portion of the semiconductor die, wherein the first bond pad is a bond pad for a first power supply voltage domain of the semiconductor die, wherein the semiconductor die has a second bond pad in the interior portion and wherein the second bond pad is a bond pad for a second power supply voltage domain of the semiconductor die;

a first conductive distributor over a first portion of the semiconductor die and contained within a perimeter of the semiconductor die,

a first bond wire connected to the first bond pad and the first conductive distributor;

a second bond wire connected to a first peripheral bond pad of the plurality of peripheral bond pads and the first conductive distributor;

a second conductive distributor over a second portion of the semiconductor die and contained within a perimeter of the semiconductor die;

a third bond wire connected between the second bond pad and the second conductive distributor; and

a fourth bond wire connected between a second peripheral bond pad of the plurality of peripheral bond pads and the second conductive distributor.

16. An integrated circuit package, comprising:

a package support;

a semiconductor die attached to the package support, wherein the semiconductor die has a plurality of peripheral bond pads along a periphery of the semiconductor die and a first bond pad on an interior portion of the semiconductor die, wherein the first bond pad is a bond pad for a first power supply voltage domain of the semiconductor die wherein the semiconductor die has a second bond pad in the interior portion and wherein the second bond pad is a bond pad for a second power supply voltage domain of the semiconductor die;

a first conductive distributor over a first portion of the semiconductor die and contained within a perimeter of the semiconductor die,

a first bond wire connected to the first bond pad and the first conductive distributor; and

a second bond wire connected to a first peripheral bond pad of the plurality of peripheral bond pads and the first conductive distributor;

a second conductive distributor over the first conductive distributor, insulated from the first conductive distributor, and setback from the first conductive distributor,

a third bond wire connected between the second bond pad and the second conductive distributor; and

a fourth bond wire connected between a second peripheral bond pad of the plurality of peripheral bond pads and the second conductive distributor.

17. The integrated circuit package of claim 14 wherein:

the package support includes a plurality of wire bonding surfaces, the plurality of wire bonding surfaces includes the wire bonding surface;

no bond wire of the integrated circuit package is connected to both a wire bonding surface of the package support and the first conductive distributor.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2010
From: LEE, CHU-CHUNG; CHIN, KIAN LEONG; HESS, KEVIN J.; JOHNSTON, PATRICK; TRAN, TU-ANH N.; YIP, HENG KEONG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 024751/0644 →