IP Library Granted Patent US 8,482,266
Granted Patent B2
US 8,482,266 · App. 13/013,220 · Granted Jul 9, 2013

Voltage regulation circuitry and related operating methods

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Quick Facts
Patent No.
US 8,482,266
App. No.
13/013,220
Granted
Jul 9, 2013
Kind
B2
Abstract

Apparatus for voltage regulation circuits and related operating methods are provided. An exemplary voltage regulation circuit includes a voltage regulation arrangement that provides a regulated output voltage based on an input voltage reference, a phase compensation arrangement coupled to the voltage regulation arrangement and configured to increase a phase margin of the voltage regulation arrangement, and detection circuitry coupled to the phase compensation arrangement. The detection circuitry is configured to disable the phase compensation arrangement in response to detecting an output current that is less than a threshold value.

Claims (84)

1. A voltage regulation circuit comprising:

a voltage regulation arrangement configured to provide an output voltage at an output node based on an input voltage reference at an input node, wherein the voltage regulation arrangement includes an amplifier arrangement configured to regulate the output voltage based on a difference between a feedback voltage and the input voltage;

a phase compensation arrangement coupled to the amplifier arrangement, the phase compensation arrangement being configured to increase a phase margin of the amplifier arrangement; and

detection circuitry coupled to the phase compensation arrangement, wherein the detection circuitry is configured to disable the phase compensation arrangement in response to detecting an output current at the output node is less than a threshold value.

2. The voltage regulation circuit of claim 1 , wherein:

the voltage regulation arrangement includes a first transistor coupled between the output node and a first node, the first transistor being configured to allow current to flow from the first node to the output node; and

the detection circuitry is configured to disable the phase compensation arrangement in a manner that is influenced by the current flowing from the first node to the output node through the first transistor.

3. The voltage regulation circuit of claim 1 , wherein:

the voltage regulation arrangement includes:

a pass device coupled between the output node and a first node, the output current comprising at least a portion of a current flowing through the pass device from the first node to the output node; and

a voltage divider arrangement coupled between the output node and a second node, the voltage divider arrangement being configured to establish the feedback voltage at a feedback voltage node;

the amplifier arrangement is coupled to the input node, the feedback voltage node, and the pass device; and,

the amplifier arrangement is configured to adjust the current flowing through the pass device based on the difference between the feedback voltage and the input voltage reference.

4. The voltage regulation circuit of claim 1 , wherein the detection circuitry is configured to enable the phase compensation arrangement in response to detecting the output current at the output node is greater than the threshold value.

5. A system including the voltage regulation circuit of claim 1 , further comprising an electronic device coupled to the output node of the voltage regulation circuit to receive the regulated output voltage.

6. A voltage regulation circuit comprising:

a voltage regulation arrangement configured to provide a regulated output voltage at an output node based on an input voltage reference at an input node, the voltage regulation arrangement including a first transistor coupled between the output node and a first node, the first transistor being configured to allow current to flow from the first node to the output node;

a phase compensation arrangement coupled to the voltage regulation arrangement, the phase compensation arrangement being configured to increase a phase margin of the voltage regulation arrangement;

a first current mirror arrangement coupled to the first transistor, the first current mirror arrangement being configured to mirror the current flowing from the first node to the output node through the first transistor to obtain a reference current flowing through the first current mirror arrangement; and

detection circuitry coupled to the first current mirror arrangement, wherein the detection circuitry is configured to disable the phase compensation arrangement in response to detecting the reference current is indicative of the output current at the output node being less than the threshold value.

7. The voltage regulation circuit of claim 6 , wherein the detection circuitry includes:

a second transistor configured to mirror the reference current flowing through the first current mirror arrangement such that a voltage across the second transistor being influenced by the reference current; and

a comparator configured to generate a first signal to disable the phase compensation arrangement when the voltage across the second transistor is greater than a threshold voltage, the threshold voltage being indicative of the output current at the output node being less than the threshold value.

8. The voltage regulation circuit of claim 7 , further comprising a switching element configured electrically parallel to the phase compensation arrangement, wherein the first signal generated by the comparator activates the switching element to disable the phase compensation arrangement.

9. The voltage regulation circuit of claim 7 , wherein the comparator is configured to generate a second signal to enable the phase compensation arrangement when the voltage across the second transistor is less than the threshold voltage.

10. The voltage regulation circuit of claim 6 , further comprising a second current mirror arrangement configured to mirror the reference current flowing through the first current mirror arrangement, wherein the second current mirror arrangement is coupled to the voltage regulation arrangement and configured to increase the regulated output voltage in a manner that is influenced by the reference current.

11. A voltage regulation circuit comprising:

an input node configured to receive an input voltage reference;

an output node;

a first node;

a second node;

a first transistor coupled between the first node and the output node, the first transistor being configured to allow an output current at the output node to flow from the first node to the output node through the first transistor;

a voltage divider arrangement coupled between the output node and the second node, the voltage divider arrangement being configured to establish a feedback voltage at a feedback voltage node;

an amplifier arrangement coupled to the input node, the feedback voltage node, and the first transistor, wherein the amplifier arrangement and the first transistor are cooperatively configured to adjust an output voltage at the output node based on a difference between the feedback voltage and the input voltage reference;

a phase compensation arrangement coupled to the amplifier arrangement;

a second transistor configured electrically parallel to the phase compensation arrangement; and

detection circuitry coupled to the second transistor, wherein the detection circuitry is configured to turn on the second transistor to disable the phase compensation arrangement in response to detecting the output current is less than a threshold value.

12. The voltage regulation circuit of claim 11 , wherein the phase compensation arrangement is configured to optimize a phase margin at a unity gain frequency of the amplifier arrangement.

13. The voltage regulation circuit of claim 11 , further comprising a first current mirror arrangement configured to mirror the output current through the first transistor to obtain a reference current, wherein:

the detection circuitry includes:

a third transistor configured to mirror the reference current through the first current mirror arrangement, a voltage across the third transistor being influenced by the reference current; and

a comparator having a first input, a second input, and an output, the first input being configured to receive the voltage across the third transistor, the second input being configured to receive a comparator reference voltage indicative of the output current being less than the threshold value, and the output being coupled to a gate terminal of the second transistor; and

the comparator is configured to generate an output signal at the output to turn on the second transistor when the voltage across the third transistor is greater than the comparator reference voltage.

14. The voltage regulation circuit of claim 11 , wherein:

the first node is configured to receive a supply voltage;

the second node is configured to receive a ground voltage;

the first transistor includes a source terminal connected to the first node and a drain terminal connected to the output node;

the amplifier arrangement comprises:

a third transistor having a gate terminal connected to the input node and a drain terminal connected to a gate terminal of the first transistor;

a fourth transistor having a drain terminal connected to the drain terminal of the third transistor and a source terminal connected to the first node; and

a fifth transistor having a gate terminal connected to the feedback voltage node and a drain terminal connected to a gate terminal of the fourth transistor; and

the phase compensation arrangement comprises:

a capacitive element connected between a source terminal of the third transistor and a source terminal of the fifth transistor; and

a resistive element connected between the source terminal of the third transistor and the source terminal of the fifth transistor.

15. The voltage regulation circuit of claim 14 , further comprising a sixth transistor having a drain terminal connected to the source terminal of the third transistor and a source terminal connected to the source terminal of the fifth transistor, wherein the detection circuitry is configured to turn on the sixth transistor in response to detecting the output current is less than the threshold value to disable the phase compensation arrangement.

16. The voltage regulation circuit of claim 15 , further comprising a first current mirror arrangement configured to mirror the output current through the first transistor to obtain a reference current, wherein the detection circuitry includes:

a seventh transistor having a source terminal connected to the second node and a gate terminal connected to the first current mirror arrangement to mirror the reference current; and

a comparator having a non-inverting input connected to a drain terminal of the seventh transistor, an inverting input configured to receive a voltage indicative of the output current being less than the threshold value, and an output connected to a gate terminal of the sixth transistor.

17. A method for operating voltage regulation circuitry including an amplifier arrangement configured to regulate an output voltage at an output node based on a difference between a feedback voltage and an input voltage reference, the method comprising:

monitoring an output current at the output node;

comparing the output current to a threshold value; and

in response to detecting the output current is less than the threshold value, disabling a phase compensation arrangement coupled to the amplifier arrangement, the phase compensation arrangement being configured to increase a phase margin of the amplifier arrangement when enabled.

18. The method of claim 17 , wherein:

monitoring the output current comprises mirroring the output current to obtain a reference current;

comparing the output current to the threshold value comprises:

mirroring the reference current with a first transistor; and

comparing a voltage across the first transistor to a reference voltage indicative of the output current being less than or equal to the threshold value, the voltage across the first transistor being influenced by the reference current; and

disabling the phase compensation arrangement comprises disabling the phase compensation arrangement when the voltage across the first transistor is greater than the reference voltage.

19. The method of claim 17 , wherein disabling the phase compensation arrangement comprises activating a switching element configured electrically parallel to the phase compensation arrangement.

20. A voltage regulation circuit comprising:

an input node configured to receive an input voltage reference;

an output node;

a first node configured to receive a supply voltage;

a second node configured to receive a ground voltage;

a first transistor coupled between the first node and the output node, the first transistor being configured to allow an output current at the output node to flow from the first node to the output node through the first transistor, the first transistor including a source terminal connected to the first node and a drain terminal connected to the output node;

a voltage divider arrangement coupled between the output node and the second node, the voltage divider arrangement being configured to establish a feedback voltage at a feedback voltage node;

an amplifier arrangement coupled to the input node, the feedback voltage node, and the first transistor, wherein the amplifier arrangement and the first transistor are cooperatively configured to adjust an output voltage at the output node based on a difference between the feedback voltage and the input voltage reference, the amplifier arrangement comprising:

a second transistor having a gate terminal connected to the input node and a drain terminal connected to a gate terminal of the first transistor;

a third transistor having a drain terminal connected to the drain terminal of the second transistor and a source terminal connected to the first node; and

a fourth transistor having a gate terminal connected to the feedback voltage node and a drain terminal connected to a gate terminal of the third transistor;

a phase compensation arrangement comprising:

a capacitive element connected between a source terminal of the second transistor and a source terminal of the fourth transistor; and

a resistive element connected between the source terminal of the second transistor and the source terminal of the fourth transistor; and

detection circuitry coupled to the phase compensation arrangement, wherein the detection circuitry is configured to disable the phase compensation arrangement in response to detecting the output current is less than a threshold value.

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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SECURITY AGREEMENT Recorded Nov 6, 2013
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To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
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To: CITIBANK, N.A., AS COLLATERAL AGENT
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From: YU, CHUANZHAO; BRIONES, LUIS J.
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