Intermediate product for a multichannel FET and process for obtaining an intermediate product
View Patent ↗An intermediate product in the manufacture of a vertical multiple-channel FET device containing alternating —Si—[(SiGe)—Si]u- stacked layers is shown, as well as a process for selectively etching the SiGe layers in such a stacked layer system, and products obtained from such selective etching. Differential Ge content is added to the successive layers to provide uniform removal of the sacrificial SiGe layers.
1. Intermediate product for the manufacture of a multiple-channel FET device, said intermediate product comprising a stack of semiconductor layers, said stack including:
(a) a first epitaxial silicon layer;
(b) a first epitaxial silicon-germanium layer which has a composition of formula Si x Ge 1−x , said first silicon-germanium layer overlying said first silicon layer;
(c 1 ) a second epitaxial silicon layer overlying said first silicon-germanium layer;
(d 1 ) a second epitaxial silicon-germanium layer overlying said second silicon layer, wherein said layer has a composition of formula Si x−y 1 Ge 1−x+y i ;
wherein layers (c 1 ) and (d 1 ) are followed in ascending order by one or more pairs of layers (c n ) and (d n ) consisting, respectively, of an epitaxial silicon layer and an epitaxial silicon-germanium layer of formula Si x−y n Ge 1−x+y n , where n is a positive integer of at least 2;
wherein, in each SiGe layer, the Ge concentration is substantially constant throughout the layer;
wherein the values y n for all values of n are chosen such that 0<y 1 <y n <y n+1 and the difference in the percentage of Ge atoms between successive SiGe layers lies in the range of 2% to 10%, such that (y n+1 −y n ) is comprised in the range 0.02 to 0.10.
2. Intermediate product as claimed in claim 1 , including:
(e) a final silicon layer overlying the last silicon-germanium layer of formula Si x−y n Ge 1−x+y n , where n is a positive integer of at least 1; and
(f) a protective layer.
3. Intermediate product according to claim 2 , wherein the protective layer is a nitride, a non-metallic oxide such as SiO 2 , a metal oxide, boron nitride or thick photoresist layer.
4. Intermediate product according to claim 1 , including an insulating layer which underlies said first silicon layer.
5. Intermediate product according to claim 4 , where the insulating layer is buried silicon oxide, or sapphire (Al 2 O 3 ).
6. Method of manufacturing a multiple-channel FET device, comprising the steps of:
(a) providing a first epitaxial silicon layer;
(b) forming over said first silicon layer a first epitaxial silicon-germanium layer which has a composition of formula Si x Ge 1−x ;
(c 1 ) forming a second epitaxial silicon layer over said first silicon-germanium layer;
(d 1 ) forming a second epitaxial silicon-germanium layer over said second silicon layer, wherein said second silicon-germanium layer has a composition of formula Si x−y 1 Ge 1−x+y 1 ;
wherein (c 1 ) and (d 1 ) are repeated to form, in ascending order, one or more pairs of layers (c n ) and (d n ) consisting, respectively, of an epitaxial silicon layer and an epitaxial silicon-germanium layer of formula Si x−y n Ge 1−x+y n , where n is a positive integer of at least 2;
wherein, in each SiGe layer, the Ge concentration is substantially constant throughout the layer;
wherein the values y n for all values of n are chosen such that 0<y 1 <y n <y n+1 and the difference in the percentage of Ge atoms between successive SiGe layers lies in the range of 2% to 10%, such that (y n+1 −y n ) is comprised in the range 0.02 to 0.10; and
(e) in the structure resulting from steps (a) to (d1), etching all the SiGe layers selectively with respect to the Si layers in a common etching process.
7. Manufacturing method according to claim 6 , where the etching step (b) involves the use of a gas or plasma phase halogen-based agent such as CF 4 and/or CH 2 F 2 .
8. Manufacturing method according to claim 6 , where the etching step (b) involves the use of an oxidizing liquid phase solution, containing one or more of HNO 3 , H 2 O 2 and HF.
9. The method of claim 6 wherein the etching includes etching the all the SiGe layers to a substantially equivalent depth.
10. The method of claim 6 further comprising:
after the etching the SiGe layers, forming a gate dielectric over exposed surfaces of silicon.
11. The method of claim 10 further comprising:
forming a gate material over the gate dielectric.
12. The method of claim 6 further comprising:
forming a source region and a drain region.
13. The method of claim 7 wherein the etching includes etching the all the SiGe layers to a substantially equivalent depth.
14. The method of claim 8 wherein the etching includes etching the all the SiGe layers to a substantially equivalent depth.
15. The method of claim 7 further comprising:
after the etching the SiGe layers, forming a gate dielectric over exposed surfaces of silicon.
16. The method of claim 8 further comprising:
after the etching the SiGe layers, forming a gate dielectric over exposed surfaces of silicon.
17. The method of claim 9 further comprising:
after the etching the SiGe layers, forming a gate dielectric over exposed surfaces of silicon.
18. The method of claim 17 further comprising:
forming a gate material over the gate dielectric.
19. The method of claim 7 further comprising:
forming a source region and a drain region.
20. The method of claim 8 further comprising:
forming a source region and a drain region.