Erase ramp pulse width control for non-volatile memory
View Patent ↗A method of erasing a memory block of a non-volatile memory, including setting a pulse width of erase pulses to an initial width, repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied, gradually adjusting a pulse voltage magnitude of the erase pulses from an initial pulse voltage level to a maximum pulse voltage level, and reducing the width of the erase pulses to less than the initial width when the pulse voltage magnitude reaches an intermediate voltage level between the initial pulse voltage level and the maximum pulse voltage level. Thus, narrow pulses are applied at higher voltage levels to reduce the amount of over erasure of the memory block.
1. A method of erasing a memory block of a non-volatile memory, comprising:
setting a pulse width of erase pulses to an initial width;
repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied;
during said repeatedly applying erase pulses to the memory block, gradually adjusting a pulse voltage magnitude of the erase pulses from an initial pulse voltage level to a maximum pulse voltage level; and
during said repeatedly applying erase pulses to the memory block, reducing the width of the erase pulses to less than the initial width when the pulse voltage magnitude reaches an intermediate voltage level between the initial pulse voltage level and the maximum pulse voltage level.
2. The method of claim 1 , further comprising performing an erase verify test after application of each erase pulse to determine whether the memory block has met the erase metric.
3. The method of claim 1 , further comprising determining whether each memory cell of the memory block has a threshold voltage which is no more than an erase verify voltage level to determine whether the memory block has met the erase metric after application of each erase pulse.
4. The method of claim 1 , wherein said gradually adjusting a pulse voltage magnitude of the erase pulses comprises:
adjusting the pulse voltage magnitude by an incremental step voltage after application of each erase pulse while the pulse voltage magnitude is less than the intermediate voltage level; and
adjusting the pulse voltage magnitude by the incremental step voltage after application of a step pulse count limit number of erase pulses while the pulse voltage magnitude is at least the intermediate voltage level, wherein the step pulse count limit number is greater than one.
5. The method of claim 4 , wherein said reducing the width of the erase pulses comprises dividing the initial width by the step pulse count limit number.
6. The method of claim 1 , wherein said gradually adjusting a pulse voltage magnitude of the erase pulses comprises:
adjusting the pulse voltage magnitude by a first incremental step voltage after application of each erase pulse while the pulse voltage magnitude is less than the intermediate voltage level; and
adjusting the pulse voltage magnitude by a second incremental step voltage after application of at least one erase pulse while the pulse voltage magnitude is at least the intermediate voltage level, wherein the second incremental step voltage is less than the first incremental step voltage.
7. A method of erasing a memory block of a non-volatile memory, comprising:
preprogramming the memory block;
erasing the memory block after said preprogramming, wherein said erasing comprises:
setting a pulse width of erase pulses to an initial width;
repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied;
during said repeatedly applying erase pulses to the memory block, gradually adjusting a pulse voltage magnitude of the erase pulses from an initial pulse voltage level to a maximum pulse voltage level; and
during said repeatedly applying erase pulses to the memory block, reducing the width of the erase pulses to less than the initial width when the pulse voltage magnitude reaches an intermediate voltage level between the initial pulse voltage level and the maximum pulse voltage level; and
when the memory block is erased, soft programming any memory cells of the memory block which have been over erased.
8. The method of claim 7 , further comprising:
setting a step pulse count limit number to an initial number which is at least one;
increasing the step pulse count limit number when the pulse voltage magnitude reaches the intermediate voltage level; and
wherein said repeatedly applying erase pulses comprises applying the step pulse count limit number of erase pulses at each pulse voltage magnitude.
9. The method of claim 8 , wherein said reducing the width of the erase pulses comprises dividing the initial width by the step pulse count limit number.
10. The method of claim 7 , wherein said gradually adjusting a pulse voltage magnitude comprises increasing the pulse voltage magnitude by an incremental step voltage, further comprising decreasing the incremental step voltage when the pulse voltage magnitude reaches the intermediate voltage level.
11. The method of claim 10 , wherein said reducing the width of the erase pulses comprises narrowing pulse width by an integer number greater than one, and wherein said method further comprises dividing the incremental step voltage by the integer number when the pulse voltage magnitude reaches the intermediate voltage level.
12. The method of claim 7 , wherein said preprogramming the memory block comprises applying at least one program pulse to each memory cell of the memory block which has a threshold voltage less than a program verify voltage until each memory cell has a threshold voltage of at least the program verify voltage.
13. The method of claim 7 , wherein said determining whether the memory block is erased comprises determining whether each memory cell of the memory block has a threshold voltage which is no greater than an erase verify voltage.
14. The method of claim 7 , wherein said soft programming comprises applying at least one soft program pulse to each memory cell of the memory block which has a threshold voltage less than a soft program verify voltage until each memory cell has a threshold voltage of at least the soft program verify voltage.
15. A non-volatile memory, comprising:
a plurality of memory cells; and
a memory control system which repeatedly applies erase pulses to said plurality of memory cells until said plurality of memory cells meets an erase metric or until a maximum number of erase pulses have been applied, wherein said memory control system incrementally increases a pulse voltage of said erase pulses from an initial pulse voltage to a maximum pulse voltage, and wherein said memory control system reduces a pulse width of said erase pulses from an initial pulse width to a narrow pulse width when said pulse voltage achieves an intermediate voltage level which is between said initial pulse voltage and said maximum pulse voltage.
16. The non-volatile memory of claim 15 , wherein said memory control system incrementally increases an erase pulse voltage applied to at least one well connection of each of said plurality of memory cells.
17. The non-volatile memory of claim 15 , wherein said memory control system increases said pulse voltage of each one of said erase pulses by an incremental voltage until said pulse voltage achieves said intermediate voltage level, and wherein said memory control system increases said pulse voltage by said incremental voltage after each group comprising a limit number of more than one erase pulse after said pulse voltage achieves said intermediate voltage level.
18. The non-volatile memory of claim 17 , wherein said memory control system determines said narrow pulse width by dividing said initial pulse width by said limit number.
19. The non-volatile memory of claim 15 , wherein said memory control system increases said pulse voltage of each one of said erase pulses by a first incremental voltage until said pulse voltage achieves said intermediate voltage level, wherein said memory control system increases said pulse voltage of each one of said erase pulses by a second incremental voltage after said pulse voltage achieves said intermediate voltage level, and wherein said second incremental voltage is less than said first incremental voltage.
20. The non-volatile memory of claim 15 , wherein said memory control system preprograms said plurality of memory cells before applying said erase pulses, and wherein said memory control system soft programs over erased ones of said plurality of memory cells after said plurality of memory cells meets said erase metric.