Static random access memory (SRAM) having bit cells accessible by separate read and write paths
A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of inverters for storing a logic state, optimized for being written, and powered by a read voltage during a read of the first plurality of bit cells. Each bit cell of the first plurality of bit cells is coupled to a true read bit line and a true write bit line, and a second plurality of bit cells is coupled to a complementary read bit line and a complementary write bit line. The true and complementary read bit lines are precharged to a precharge voltage of about half the read voltage. The true read bit line is predisposed to a logic low condition. One of a group consisting of a high impedance from the first bit cell to indicate that the logic state is a logic low and a signal voltage greater than the intermediate voltage to indicate that the logic state is a logic high is output from the first bit cell to the true read bit line.
1. A static random access memory having bit cells connected to different paths for reading than for writing, comprising:
a first plurality of bit cells in a first row coupled to a true read bit line and a true write bit line;
a first bit cell of the plurality of bit cells coupled to a first read word line and a first write word line and is selected for reading when the first read word line is enabled, wherein the first bit cell provides a high impedance to the true read bit line when the first bit cell is outputting a first logic state and provides a signal voltage on the true read bit line when the first bit cell is outputting a second logic state, wherein the first logic state is different from the second logic state;
a second plurality of bit cells in a second row coupled to a complementary read bit line and a complementary write bit line, wherein the first plurality of bit cells and the second plurality of bit cells are powered by a voltage applied between a first power supply terminal at a first voltage and a second power supply terminal at a second voltage during a read;
a precharge circuit that precharges, prior to a read, the true read bit line and the complementary read bit line to a precharge voltage intermediate the first voltage and the second voltage, wherein the precharge voltage is less than the signal voltage;
a dummy cell coupled to the true read bit line that draws charge from the true read bit line when any one of the first plurality of bit cells is selected for reading, wherein when the first bit cell is storing the first logic state the dummy cell causes a predisposition in voltage on the true read bit line; and
a sense amplifier coupled to the true read bit line and the complementary read bit line that amplifies a difference between a voltage present on the true read bit line and a voltage present on the complementary read bit line during a read.
2. The memory of claim 1 , wherein the first bit cell comprises:
a pair of cross coupled inverters having a first input/output and a second input/output;
a first transistor having a control electrode coupled to the first write word line, a first current electrode coupled to the true write bit line, and a second current electrode coupled to the first input/output;
a source follower having an input coupled to the second input/output and an output;
a second transistor having a first current electrode coupled to the output of the source follower, a control electrode coupled to the first read word line, and a second current electrode coupled to the true read bit line.
3. The memory of claim 2 , wherein the source follower of the first bit cell comprises a third transistor having a first current electrode coupled to a reference voltage, a gate as the input of the source follower, and a second current electrode as the output of the source follower.
4. The memory of claim 3 , wherein the reference voltage is greater than the intermediate voltage and less than the first voltage.
5. The memory of claim 4 , wherein the intermediate voltage is halfway between the first voltage and the second voltage.
6. The memory of claim 5 , wherein the second voltage is ground.
7. The memory of claim 1 , wherein the dummy cell comprises a capacitor.
8. The memory of claim 7 , wherein the dummy cell is further characterized by the capacitor being coupled to the true read bit line during a read of the first plurality of memory cells and being discharged after a read of the first plurality of memory cells.
9. The memory of claim 8 , further comprising a second dummy cell comprising a second capacitor wherein the second capacitor is coupled to the complementary read bit line during a read of the second plurality of bit cells and being discharged after the read of the second plurality of bit cells.
10. The memory of claim 1 , wherein the second voltage is ground and the intermediate voltage is halfway between the first voltage and ground.