Near zero channel length field drift LDMOS
View Patent ↗Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space ( 52, 152 ) adjacent the drain ( 56, 156 ), is avoided by providing a lightly doped region ( 511, 1511 ) of a first conductivity type (CT) separating the first CT drift space ( 52, 152 ) from an opposite CT WELL region ( 53, 153 ) in which the first CT source ( 57, 157 ) is located, and a further region ( 60, 160 ) of the opposite CT (e.g., formed by an angled implant) extending through part of the WELL region ( 53, 153 ) under an edge ( 591, 1591 ) of the gate ( 59, 159 ) located near a boundary ( 531, 1531 ) of the WELL region ( 53, 153 ) into the lightly doped region ( 511, 1511 ), and a shallow still further region ( 66, 166 ) of the first CT Ohmically coupled to the source ( 57, 157 ) and ending near the gate edge ( 591, 159 ) whereby the effective channel length ( 61, 161 ) in the further region ( 60, 160 ) is reduced to near zero. Substantial improvement in BVDSS and/or Rdson can be obtained without degrading the other or significant adverse affect on other device properties.
1. A field LDMOS device, comprising:
a semiconductor body having a first surface, and having therein a drift space of a first conductivity type with a first edge extending to the first surface and a WELL region of a second, opposite, conductivity type with a second edge extending to the first surface, the first and second edges being laterally separated by a first conductivity type part of the semiconductor body;
a source and drain of the first conductivity type in the semiconductor body, the source being located in the WELL region and the drain being located in the drift space;
an insulated gate located over the semiconductor body, the gate having a third edge toward the source and a fourth edge toward the drain;
a doped further region of the second conductivity type extending across a part of the WELL region and under the third edge and having a fifth edge in the part of the semiconductor body; and
a doped still further region of the first conductivity type in the further region, in Ohmic contact with the source, having a sixth edge laterally proximate the third edge and separated from the fifth edge by a part of the further region adapted to form therein a field induceable conductive channel of the first conductivity type, the field induceable channel having a channel length laterally bounded by the fifth and the sixth edges.
2. The LDMOS device of claim 1 , wherein the channel length is in the range of about 0.005 to 0.20 micrometers.
3. The LDMOS device of claim 1 , wherein the further region is formed by an angled implant.
4. The LDMOS device of claim 1 , wherein the further region is formed by an angled implant using the gate at least in part as a mask therefore.
5. The LDMOS device of claim 3 , wherein the angled implant is performed at an angle α with respect to a normal to the first surface in a range of about 10≦α≦70 degrees.
6. The LDMOS device of claim 1 , wherein the further region and the still further region are formed using a common masking edge.
7. The LDMOS device of claim 1 , wherein the further region has a further region doping concentration C FR , and the still further region has a still further region doping concentration C SFR and C SFR >C FR .
8. The LDMOS device of claim 1 , wherein the further region has a further region doping concentration C FR , and the part of the semiconductor body has a doping concentration C PSCB , and the ratio C FR /C PSCB is in the range from about 10 1 to about 10 8 .
9. A semiconductor device, comprising:
a semiconductor (SC) body having a first surface and comprising a SC region of a first conductivity type extending to the first surface;
a WELL region of a second, opposite, conductivity type extending into the SC region beneath the first surface and having a first boundary extending to the first surface;
a drift space of the first conductivity type extending into the SC region beneath the first surface and having a second boundary extending to the first surface, the second boundary being spaced apart from the first boundary by a part of the SC region;
a gate formed over and separated from the first surface by a gate insulator, the gate having a first edge laterally substantially proximate the first boundary and a second edge spaced apart from the first boundary;
a source of the first conductivity type in the WELL region spaced apart from the first edge;
a drain of the first conductivity type in the drift space;
a further region of the second conductivity type in the WELL region and having a third boundary beyond the first edge a predetermined lateral distance greater than zero from the first boundary into the part of the SC region; and
a still further region of the first conductivity type in the further region in Ohmic contact with the source and having a fourth boundary separated from the third boundary by a length in the further region adapted when subject to an electric field to form a channel of the first conductivity type within the part of the SC region and laterally bound by the fourth boundary of the still further region and the third boundary of the further region.
10. The semiconductor device of claim 9 , wherein the still further region has a doping concentration C SFR in the range of about 1E19 to 1E20 cm −3 .
11. The semiconductor device of claim 10 , wherein the part of the SC region has a doping concentration C PSCR in the range of about 1E13 to 1E16 cm −3 .
12. The semiconductor device of claim 11 , wherein the further region has a doping concentration C FR in the range of about 1E18 to 5E20 cm −3 .
13. The semiconductor device of claim 9 , wherein the still further region has a doping concentration C SFR and wherein the further region has a doping concentration C FR and a ratio C SFR /C FR lies between about 2 to 10 2 .
14. The semiconductor device of claim 9 , wherein the fourth boundary of the still further region is substantially laterally aligned with the first edge of the gate.
15. The semiconductor device of claim 14 , wherein the first boundary of the WELL region is substantially laterally aligned with the fourth boundary of the still further region and the first edge of the gate.
16. The semiconductor device of claim 9 , wherein the length of the channel is between about 0.005 and about 0.20 micrometers.
17. The semiconductor device of claim 16 , wherein the length of the channel is between about 0.05 and about 0.075 micrometers.
18. The semiconductor device of claim 9 , further comprising a shallow trench isolation (STI) region in the drift space at least partly underlying the gate and extending substantially to the drain.
19. The semiconductor device of claim 9 , wherein the doping concentration of the part of the SC region, as taken at the terminus of the channel, is less than the doping concentration of the drift space.