LEAD FRAME WITH RECESSED DIE BOND AREA
A lead frame having a recessed die bond area. The lead frame has top and bottom surfaces and a first lead frame thickness defined as the distance between the top and bottom surfaces. The lead frame has a die bond area surface located within a reduced die bond area. A second thickness is defined as the distance between the die bond area surface and the bottom surface. The second lead frame thickness is less than the first lead frame thickness such that a semiconductor die disposed and attached to the die bond area surface has a reduced overall package thickness. A side wall formed between the die bond area surface and the top surface contains the adhesive material used to attach the die, which reduces adhesive bleeding and prevents wire bonding contamination.
1 . A lead frame for receiving and being electrically connected to a semiconductor die, the lead frame comprising:
a top surface and a bottom surface, wherein a first lead frame thickness is defined as the distance between the top and bottom surfaces;
a reduced die bond area in the top surface for receiving a semiconductor die, the reduced die bond area having a die bond area surface located between the top surface and the bottom surface and a side wall extending around a perimeter of the die bond area surface to the top surface, wherein a distance between the die bond area surface and the bottom surface defines a second lead frame thickness that is less than the first lead frame thickness; and
a plurality of conductive regions arranged around and spaced apart from the die bond area surface.
2 . The lead frame of claim 1 , wherein the second lead frame thickness is half the first lead frame thickness.
3 . The lead frame of claim 1 , wherein the second lead frame thickness is less than half the first lead frame thickness.
4 . The lead frame of claim 1 , wherein the die bond area surface and the side wall are dimensioned to receive adhesive material used to attach a semiconductor die to the die bond area surface within the reduced die bond area and containing the adhesive material within the reduced die bond area to prevent bleeding of the adhesive material so that the adhesive material does not contaminate the top surface of the lead frame and the plurality of conductive regions.
5 . The lead frame of claim 1 , wherein the top surface and the die bond area surface are lie on parallel planes.
6 . The lead frame of claim 1 , wherein the side wall is perpendicular to the top surface and the die bond area surface.
7 . The lead frame of claim 1 , wherein the side wall is sloped between the top surface and the die bond area surface.
8 . A semiconductor die package comprising:
a lead frame having a top surface and a bottom surface, wherein a first lead frame thickness is defined as the distance between the top surface and the bottom surface, the lead frame having a reduced die bond area in the top surface, the reduced die bond area having a die bond area surface located between the top surface and the bottom surface and a side wall extending around a perimeter of the die bond area surface to the top surface, the die bond area surface and the bottom surface defining a second lead frame thickness that is less than the first lead frame thickness, the lead frame having a plurality of conductive regions arranged around and spaced apart from a perimeter of the die bond area surface;
a semiconductor die having a first surface and a second surface, the first surface attached to the die bond area surface within the reduced die bond area, and the second surface having a plurality of die bond pads for electrical interconnection with at least one of the plurality of conductive regions; and
an encapsulation material that at least partially encapsulates the semiconductor die and the lead frame.
9 . The semiconductor die package of claim 8 , further comprising wires electrically connecting the die bond pads and the conductive regions.
10 . The semiconductor die package of claim 8 , wherein the wires are wire bonded to the die bond pads and the conductive regions.
11 . The semiconductor die package claim 8 , wherein the second lead frame thickness is half the first lead frame thickness.
12 . The semiconductor die package of claim 8 , wherein the second lead frame thickness is less than half the first lead frame thickness.
13 . The semiconductor die package of claim 8 , wherein the die bond area surface and the side wall are dimensioned to receive an adhesive material, the adhesive material for attaching the semiconductor die to the die bond area surface and contain the adhesive material so that the adhesive material does not bleed onto the plurality of conductive regions.
14 . The semiconductor die package of claim 8 , wherein the top surface and the die bond area surface are parallel.
15 . The semiconductor die package of claim 8 , wherein the side wall is perpendicular to the top surface and the die bond area surface.
16 . A method of a packaging a semiconductor die, comprising the steps of:
providing a lead frame having a top surface and a bottom surface, wherein a first lead frame thickness is defined as a distance between the top surface and the bottom surface, the lead frame including a reduced die bond area in the top surface for receiving a semiconductor die, the reduced die bond area having a die bond area surface and a side wall extending around a perimeter of the die bond area surface to the top surface, wherein a second lead frame thickness that is less than the first lead frame thickness is defined as a distance between the die bond area surface and the bottom surface, and the lead frame further including a plurality of conductive regions arranged around and spaced apart from the perimeter of the reduced die bond area.
17 . The method of packaging a semiconductor die of claim 16 , further comprising attaching a first surface of a semiconductor die to the die bond area surface with an adhesive.
18 . The method of packaging a semiconductor die of claim 17 , further comprising:
electrically connecting the semiconductor die with the conductive regions of the lead frame; and
encapsulating the lead frame and the semiconductor die with an encapsulation material.
19 . The method of packaging a semiconductor die of claim 17 , further comprising reducing the thickness of the semiconductor die before attaching the semiconductor die to the die bond area surface.
20 . The method of claim 19 , wherein the reducing the thickness of the semiconductor die is by back grinding.