Granted Patent B2

US 8,198,916 · App. 12/871,864 · Granted Jun 12, 2012

Abstract

Claims (29)

1. A digital signal voltage level shifter, comprising:

an edge detector for detecting assertion of a digital input signal from a first logic circuit in a source voltage domain;

an output module triggered by said edge detector for asserting a digital output signal corresponding to said digital input signal for a second logic circuit in a destination voltage domain, wherein the edge detector and the output module are supplied with power only from a power supply of the destination voltage domain; and

a reset generator connected to the output module for asserting a reset signal in response to subsequent de-assertion of the digital input signal, wherein the reset generator is supplied with power only from the power supply of the destination voltage domain;

wherein said reset generator comprises:

a first switch that is OFF when the digital output signal is de-asserted or the digital input signal is de-asserted, and is ON when said digital output signal is asserted and the digital input signal is asserted;

a capacitor charged by the digital input signal through the first switch when the first switch is ON;

a second switch that is OFF when the digital input signal is asserted and ON when said digital input signal is de-asserted to conduct a charge on the capacitor; and

a third switch that is OFF when the second switch is OFF to enable de-assertion of the reset signal and is ON in response to the charge on the capacitor so as to assert the reset signal when the second switch is ON, and wherein the first and second switches are arranged to prevent leakage of the digital input signal to the destination voltage domain power supply when either of the first and second switches is OFF, and

wherein the edge detector asserts a set signal in response to the assertion of the digital input signal, and the output module asserts the digital output signal in response to assertion of the set signal and de-asserts the digital output signal in response to the reset signal.

2. The digital signal voltage level shifter of claim 1 , wherein the output module comprises an output latch that is set by assertion of the set signal and reset by assertion of the reset signal.

3. A digital signal voltage level shifter, comprising:

an edge detector for detecting assertion of a digital input signal from a first logic circuit in a source voltage domain;

an output module triggered by said edge detector for asserting a digital output signal corresponding to said digital input signal for a second logic circuit in a destination voltage domain, wherein the edge detector and the output module are supplied with power only from a power supply of the destination voltage domain;

a trigger that is activated for detecting the assertion of the digital input signal;

an edge detector latch set by the trigger for triggering the output module to assert the digital output signal; and

a de-activator for de-activating the trigger when the digital output signal is asserted.

4. A method of shifting a voltage level of a digital input signal generated in a source voltage domain from a first voltage level to a second voltage level, wherein the source voltage domain operates at the first voltage level, the method comprising the steps of:

detecting a leading edge of the digital input signal with an edge detector;

triggering assertion of a digital output signal in response to detection of the leading edge of the digital input signal with an output circuit; and

providing the digital output signal to a destination circuit in a destination voltage domain, wherein the destination voltage domain operates at a second voltage level that is higher than the first voltage level, and wherein the edge detector and the output circuit are provided power only from the destination voltage domain,

wherein a set signal is asserted in response to detection of the leading edge of the digital input signal, a reset signal generated by a reset generator that is asserted in response to subsequent de-assertion of the digital input signal, and the digital output signal is asserted in response to assertion of the set signal and de-asserted in response to the reset signal, wherein the reset generator is supplied with power only from the destination voltage domain, and

wherein the edge detection includes:

turning OFF a first switch when the digital output signal is de-asserted and/or the digital input signal is de-asserted, turning ON the first switch when the digital output signal is asserted and the digital input signal is asserted;

charging a capacitor with the digital input signal via the first switch when ON;

turning OFF a second switch when the digital input signal is asserted and turning ON the second switch to conduct a charge on the capacitor when the digital input signal is de-asserted; and

turning OFF a third switch when the second switch is OFF to enable de-assertion of the reset signal and turning ON the third switch in response to said charge on said capacitor so as to assert the reset signal when the second switch is ON, wherein the first and second switches prevent leakage of the digital input signal to the power supply of said destination voltage domain when either of the first and second switches is OFF.

5. The method of shifting a digital signal voltage level of claim 4 , wherein the output signal assertion comprises setting an output latch by asserting the set signal and resetting the output latch by asserting the reset signal.

6. The method of shifting a digital signal voltage level of claim 5 , wherein the edge detection includes activating a trigger for detecting the assertion of the digital input signal, wherein an edge detector latch is set by the trigger for triggering the digital output signal assertion, and de-activating the trigger when the digital output signal is asserted.

Assignments (29)