Memory controller address and data pin multiplexing
View Patent ↗A system and a method for configuring a memory controller that communicates with a memory device muxes selected pins for the data transfer. The memory controller includes a set of pins where each pin of the set is associated with a data bit and an address bit. A programmable logic block is connected to the set of pins and uses a subset of the set of pins to enable data transfer between the memory device and the memory controller depending on the size of the memory device such that the pins not included in the subset are available for other applications.
1. A system for configuring a memory controller, the memory controller suitable for communicating with a memory device, the memory controller including a set of pins, each pin of the set of pins being associated with at least one of a data bit and an address bit, the system comprising:
a programmable logic block connected to the set of pins of the memory controller, the programmable logic block selecting a subset of the set of pins to enable data transfer between the memory device and the memory controller, wherein the selection of the subset is performed by re-organizing one or more address bits among the set of pins of the memory controller in accordance with the size of the memory device;
a multiplexer connected to the programmable logic block for multiplexing address and data bits; and
a latch connected between the multiplexer and the memory device, the latch latching the multiplexed address and data bits on a plurality of pins from the subset of pins to transfer address and data bits between the memory device and the memory controller, wherein each of the latch and the multiplexer includes a control pin for receiving a control signal indicating multiplexing of address and data bits, wherein the control signal indicates a transfer of one of the address bits and the data bits, wherein multiplexing address and data bits on a plurality of pins comprises multiplexing one or more most significant bits (HSBs) of the address bits with data bits.
2. The system of claim 1 , wherein multiplexing address and data bits on a plurality of pins comprises multiplexing one or more least significant bits (LSBs) of the address bits with the data bits.
3. The system of claim 1 , wherein the programmable logic block comprises an address shifting block for re-organizing one or more address bits among the set of pins of the memory controller by left shifting the one or more address bits in accordance with the size of the memory device.
4. The system of claim 1 , wherein the programmable logic block comprises an address shifting block for re-organizing one or more of the address bits among the set of pins of the memory controller by right shifting the one or more of the address bits in accordance with the size of the memory device.
5. The system of claim 1 , wherein the programmable logic block comprises a selector for selecting a second subset of pins for communicating with one or more other applications, the communication being performed using remaining ones of the re-organized address bits, wherein the remaining ones of the re-organized address bits correspond to the second subset of pins.
6. A method for configuring a memory controller that communicates with a memory device, the memory controller including a set of pins, each pin of the set of pins being associated with at least one of a data bit and an address bit, the method comprising:
selecting a subset of the set of pins to enable data transfer between the memory device and the memory controller, the selection of the subset being performed by re-organizing address bits among the set of pins of the memory controller in accordance with the size of the memory device; and
multiplexing address bits and data bits on a plurality of pins of the subset of pins to transfer data between the memory device and the memory controller, wherein multiplexing the address and data bits on a plurality of pins comprises multiplexing one or more most significant bits (HSBs) of the address bits with data bits.
7. The method of claim 6 , wherein multiplexing of address and data bits is controlled with a control signal that indicates the transfer of one of the address bits and the data bits.
8. The method of claim 6 , wherein multiplexing the address and data bits on a plurality of pins comprises multiplexing one or more least significant bits (LSBs) of the address bits with the data bits.
9. The method of claim 6 , wherein re-organizing address bits among the set of pins of the memory controller comprises left shifting one or more of the address bits in accordance with the size of the memory device.
10. The method of claim 6 , wherein re-organizing address bits among the set of pins of the memory controller comprises right shifting one or more of the address bits in accordance with the size of the memory device.
11. The method of claim 6 , wherein the data transfer between the memory device and the memory controller comprises reading data from the memory device.
12. The method of claim 6 , wherein the data transfer between the memory device and the memory controller comprises writing data from the memory controller to the memory device.