Granted Patent B2

US 8,750,431 · App. 13/143,863 · Granted Jun 10, 2014

Abstract

Claims (35)

1. A logarithmic detector for extracting a digital data signal from a received input signal, comprising:

a plurality of detection stages;

a summator;

a data slicer;

an average filter;

wherein said plurality of detection stages is connected to said summator for providing a summation signal as a logarithmic representation of said input signal to a first input of said data slicer and an input of said average filter, said average filter having an output connected to a second input of said data slicer;

said data slicer having a data slicer output for providing an extracted digital data signal in dependence on a comparison of said summation signal and an output signal of said average filter;

said average filter receiving a first pre-charge voltage and a second pre-charge voltage depending on an output signal of a carrier detector circuit detecting a carrier signal of said input signal, wherein said second pre-charge voltage depends on a modulation depth of said input signal.

2. The logarithmic detector as claimed in claim 1 , wherein said first pre-charge voltage is a voltage level present at said input of said average filter after said carrier detector output signal first indicates a presence of said carrier signal.

3. The logarithmic detector as claimed in claim 2 , wherein said second pre-charge voltage defines an output voltage of said average filter close to an average voltage of said summation signal when said carrier detector output signal indicates a first rising edge of said input signal.

4. The logarithmic detector as claimed in claim 1 , wherein said second pre-charge voltage defines an output voltage of said average filter close to an average voltage of said summation signal when said carrier detector output signal indicates a first rising edge of said input signal.

5. The logarithmic detector as claimed in claim 4 , wherein said second pre-charge is applied to said average filter delayed by a delay time after indication of said first rising edge.

6. The logarithmic detector as claimed in claim 5 , wherein said delay time depends on a detector path delay of said detection stages.

7. The logarithmic detector as claimed in claim 1 , wherein said summation signal has an essentially constant maximum output level.

8. The logarithmic detector as claimed in claim 1 , wherein said carrier detector circuit has a carrier detection threshold depending on an offset voltage.

9. The logarithmic detector as claimed in claim 1 , wherein said carrier detector circuit comprises a switch for connecting an input of said carrier detector circuit to one of said plurality of detection stages.

10. A method of pre-charging an average filter of a logarithmic detector, said detector comprising a plurality of detection stages connected to a summator for providing a summation signal as a logarithmic representation of an input signal, said method comprising

receiving said input signal;

applying a first pre-charge voltage to said average filter depending on an output signal of a carrier detector circuit;

applying a second pre-charge voltage to said average filter depending on said output signal of said carrier detector circuit, wherein said second pre-charge voltage depends on a modulation depth of said input signal; and

extracting a digital data signal from a comparison of said summation signal and an average filter output signal.

11. The method as claimed in claim 10 , wherein said first pre-charge voltage is a voltage level present at an input of said average filter after a presence of a carrier signal of said input signal is first indicated.

12. The method as claimed in claim 11 , wherein said second pre-charge voltage defines an output voltage of said average filter close to an average voltage of said summation signal when a first rising edge of said input signal is indicated.

13. The method as claimed in claim 10 , wherein said second pre-charge voltage defines an output voltage of said average filter close to an average voltage of said summation signal when a first rising edge of said input signal is indicated.

14. The method as claimed in claim 13 , wherein said second pre-charge voltage is applied to said average filter delayed by a delay time after indication of said first rising edge.

15. The method as claimed in claim 14 , wherein said delay time depends on a detector path delay of said detection stages.

16. A receiver, comprising a logarithmic detector as claimed in claim 14 .

17. A method of pre-charging an average filter of a logarithmic detector, said detector comprising a plurality of detection stages connected to a summator for providing a summation signal as a logarithmic representation of an input signal, said method comprising

receiving said input signal;

applying a first pre-charge voltage to said average filter depending on an output signal of a carrier detector circuit;

applying a second pre-charge voltage to said average filter depending on said output signal of said carrier detector circuit, wherein said second pre-charge voltage defines an output voltage of said average filter close to an average voltage of said summation signal when a first rising edge of said input signal is indicated; and

extracting a digital data signal from a comparison of said summation signal and an average filter output signal.

18. The method as claimed in claim 17 , wherein said first pre-charge voltage is a voltage level present at an input of said average filter after a presence of a carrier signal of said input signal is first indicated.

19. The method as claimed in claim 17 , wherein said second pre-charge voltage is applied to said average filter delayed by a delay time after indication of said first rising edge.

20. The method as claimed in claim 17 , wherein said second pre-charge voltage depends on a modulation depth of said input signal.

Assignments (30)