IP Library Granted Patent US 8,264,082
Granted Patent B2
US 8,264,082 · App. 13/208,221 · Granted Sep 11, 2012

Semiconductor devices with low resistance back-side coupling

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Quick Facts
Patent No.
US 8,264,082
App. No.
13/208,221
Granted
Sep 11, 2012
Kind
B2
Abstract

Electronic elements with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes, preferably dielectric lined, in front sides of substrates, filling the trenches or pipes with a conductor having a coefficient of expansion not too different from that of the substrate but of higher conductivity, forming an epitaxial SC layer over the front side of the substrate in Ohmic contact with the conductor the trenches or pipes, forming various semiconductor (SC) devices in the epi-layer, back grinding the substrate to expose bottoms of the conductor filled trenches or pipes, and providing a back-side conductor contacting the conductor in the trenches or pipes. For silicon SCs, tungsten is a suitable conductor for filling the trenches or pipes to minimize substrate stress. Series ON-resistance of the elements due to the substrate resistance is substantially reduced.

Claims (32)

1. An electronic element having a front-side and a final backside and having one or more electronic devices proximate the front-side from which current flows to the final backside of the element, comprising:

a substrate having an upper surface and having an initial lower surface and having a final lower surface forming the final backside, the final lower surface being displaced from the initial lower surface, and one or more conductor filled pipes or trenches electrically coupled to the one or more electronic devices and extending between the upper surface and the final backside for substantially conducting the current flowing from the one or more electronic devices to the final backside of the element;

an epitaxial layer on the upper surface and over the one or more conductor filled trenches extending from the upper surface to the front side of the element, such epitaxial layer being adapted to substantially contain the one or more electronic devices; and

wherein the one or more conductor filled pipes or trenches, the epitaxial layer and the one or more electronic devices are substantially formed prior to removing material from the initial lower surface to form the final backside.

2. The electronic element of claim 1 , further comprising one or more isolation walls or separators formed from further conductor filled trenches extending at least from the upper surface to the final backside.

3. The electronic element of claim 2 , wherein at least some of the one or more isolation walls or separators lie laterally outside of the one or more electronic devices.

4. The electronic element of claim 3 , wherein at least some of the one or more isolation walls extend substantially between the final backside and the front-side of the electronic element.

5. The electronic element of claim 1 , wherein the conductor filled trenches have an insulating liner.

6. An electronic element comprising:

a thinned substrate comprising a semiconductor, wherein the thinned substrate had an initial thickness between an initial first surface and an opposed initial second surface prior to thinning, and the thinned substrate has a final thickness between the initial first surface and a new second surface less than the initial thickness due to removal of material from the initial second surface after thinning;

one or more pipes or trenches previously extending into the initial substrate from the initial first surface by a distance less than the initial thickness and greater than the final thickness, wherein the pipes or trenches are filled with a conductor to form conductor filled pipes or trenches, and one or more lower faces of the conductor in the conductor filled pipes or trenches is exposed at and coplanar with the new second surface;

a semiconductor layer over the initial first surface and the conductor filled pipes or trenches, wherein the semiconductor layer comprises a region adapted for device formation and having a new first surface;

one or more semiconductor devices formed in the device region; and

a conductor supported by the new second surface making Ohmic contact to the one or more lower faces of the conductor in the conductor filled pipes or trenches.

7. The electronic element of claim 6 , wherein the pipes or trenches are conformally coated with a dielectric comprising layer.

8. The electronic element of claim 7 , wherein the dielectric comprising layer comprises a first electrically insulating layer and a second barrier layer.

9. The electronic element of claim 8 , wherein the second barrier layer comprises nitrogen.

10. The electronic element of claim 9 , wherein the second barrier layer further comprises titanium.

11. The electronic element of claim 7 , wherein the dielectric comprising layer is coated with a further layer adapted to act as a seed layer for localized deposition of the conductor.

12. The electronic element of claim 6 , wherein the thinned substrate has a first thermal coefficient of expansion (TCE 52 ) and the conductor has a second thermal coefficient of expansion (TCE 54 ) and a ratio R=(TCE 54 )/(TCE 52 ) is less than or equal about 3.

13. The electronic element of claim 12 , wherein R is less than or equal about 2.

14. The electronic element of claim 13 , wherein R is less than or equal about 1.5.

15. The electronic element of claim 6 , wherein the conductor comprises tungsten.

16. The electronic element of claim 6 , further comprising a barrier region above the conductor in the conductor filled pipes or trenches adapted to prevent direct contact between the conductor and the semiconductor layer.

17. The electronic element of claim 16 , wherein the barrier region is electrically conductive.

18. An electronic device comprising:

a thinned substrate which had an initial thickness between a front surface and an initial back surface prior to thinning the substrate, and the thinned substrate has a final thickness, after thinning, between the front surface and a final back surface, wherein the final thickness is less than the initial thickness due to removal of material from the initial back surface during thinning;

conductor filled vias previously extending, prior to thinning the substrate, substantially from the front surface part-way through the substrate to a predetermined thickness from the initial back surface, wherein one or more lower faces of the conductor filled vias is exposed at and coplanar with the final back surface;

a semiconductor layer overlying the front surface and the conductor filled vias;

one or more devices in the semiconductor layer; and

an electrical conductor in Ohmic contact with the one or more of the conductor filled vias exposed on the final back surface.

19. The electronic device of claim 18 , further comprising an electrically conductive barrier region interposed between the semiconductor layer and the conductor filled vias.

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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