High efficiency amplifier with reduced parasitic capacitance
View Patent ↗A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
1. An electronic device, comprising:
a semiconductor substrate of a first conductivity type and having a first surface;
spaced-apart first buried layer (BL) regions of a second, opposite, conductivity type and BL doping concentration, located within the substrate and spaced apart from the first surface;
contact sinker regions of the second, opposite, conductivity type, extending substantially from the first surface to the spaced-apart first BL regions and adapted to facilitate individual electrical contact to the spaced-apart first BL regions; wherein
a first portion of the semiconductor substrate underlying the spaced-apart first BL regions has a first doping concentration less than the BL doping concentration; and
a second portion of the semiconductor substrate underlying the first portion has a second doping concentration less than the first doping concentration.
2. The electronic device of claim 1 , wherein the second doping concentration corresponds to a resistivity equal or greater than about 500 Ohm-cm.
3. The electronic device of claim 1 , further comprising:
one or more unit amplifiers located in the substrate separated from the spaced-apart first BL regions;
one or more first lateral dielectric filled trench (DFT) isolation walls, each first lateral DFT isolation wall laterally surrounding one of the one or more unit amplifiers;
at least one second lateral DFT isolation wall, surrounding collectively the one or more first lateral DFT isolation walls;
a further semiconductor region of the same conductivity type as the substrate and lying between the first and second lateral DFT isolation walls proximate the first surface; and wherein
the further semiconductor region is electrically isolated from the substrate.
4. The electronic device of claim 3 , wherein the further semiconductor region is electrically isolated from the substrate by further buried layer (BL) regions of the second, opposite, conductivity type, electrically isolated from the first BL regions and the one or more unit amplifiers.
5. The electronic device of claim 4 , wherein the first portion of the semiconductor substrate extends beneath the further BL regions.
6. The electronic device of claim 1 , further comprising:
one or more unit amplifiers located in the substrate separated from the spaced-apart first BL regions; and
one or more first lateral dielectric filled trench (DFT) isolation walls, each first lateral DFT isolation wall laterally surrounding one of the one or more unit amplifiers.
7. The electronic device of claim 6 , wherein the first lateral DTF isolation walls extend from the first surface to at least the semiconductor substrate.
8. The electronic device of claim 6 , wherein the one or more unit amplifiers each comprise:
a collector region of the second, opposite conductivity type;
a base region of the first conductivity type located in the collector region;
an emitter region of the second, opposite conductivity type located within the base region; and
a first buried layer (BL) region of the second, opposite conductivity type separating the collector region from the first semiconductor layer and extending laterally between the first lateral DFT isolation walls surrounding each unit amplifying cell.
9. The electronic device of claim 6 , further comprising:
at least one second lateral DFT isolation wall, surrounding collectively the one or more first lateral DFT isolation walls.
10. An electronic device, comprising:
a semiconductor substrate having a first doping concentration;
a first semiconductor layer overlying the semiconductor substrate and having a first conductivity type and a second doping concentration that is greater than the first doping concentration;
a second semiconductor layer overlying the first semiconductor layer and having the first conductivity type and a first surface;
spaced-apart first buried layer (BL) regions of a second, opposite conductivity type and BL doping concentration, located between the first and second semiconductor layers and spaced apart from the first surface; and
contact sinker regions of the second, opposite conductivity type, extending substantially from the first surface to the spaced-apart first BL regions and adapted to facilitate individual electrical contact to the spaced-apart first BL regions.
11. The electronic device of claim 10 , wherein the second doping concentration is less than the BL doping concentration.
12. The electronic device of claim 10 , wherein the semiconductor substrate has the first conductivity type.
13. The electronic device of claim 10 , wherein the semiconductor substrate has the second, opposite conductivity type.
14. The electronic device of claim 10 , further comprising:
one or more unit amplifiers located in the substrate separated from the spaced-apart first BL regions; and
one or more first lateral dielectric filled trench (DFT) isolation walls, each first lateral DFT isolation wall laterally surrounding one of the one or more unit amplifiers.
15. The electronic device of claim 14 , wherein the first lateral DTF isolation walls extend from the first surface to at least the semiconductor substrate.
16. The electronic device of claim 14 , wherein the one or more unit amplifying cells each comprise:
a collector region of the second, opposite conductivity type;
a base region of the first conductivity type located in the collector region;
an emitter region of the second, opposite conductivity type located within the base region; and
a first buried layer (BL) region of the second, opposite conductivity type separating the collector region from the first semiconductor layer and extending laterally between the first lateral DFT isolation walls surrounding each unit amplifying cell.
17. The electronic device of claim 14 , wherein the first lateral DFT isolation walls have a polycrystalline semiconductor core.
18. The electronic device of claim 14 , further comprising:
at least one second lateral DFT isolation wall, surrounding collectively the one or more first lateral DFT isolation walls; and
a further semiconductor region of the first conductivity type and lying between the first and second lateral DFT isolation walls, wherein the further semiconductor region is electrically isolated from the substrate by a portion of the first semiconductor layer.
19. The electronic device of claim 18 , wherein the second lateral DTF isolation wall extends from the first surface to at least the semiconductor substrate.
20. The electronic device of claim 10 , wherein the semiconductor substrate is of high resistivity.