Granted Patent B2

US 8,278,988 · App. 12/997,104 · Granted Oct 2, 2012

Abstract

Claims (28)

1. A semiconductor device comprising:

timer logic for generating a first modulated waveform signal;

delay logic operably coupled to the timer logic and arranged to provide a first delay in a rising edge of the first modulated waveform signal generated by the timer logic and provide a second delay in a falling edge of the first modulated waveform signal generated by the timer logic, such that the first delay and second delay of the first modulated waveform signal form a second, refined modulated waveform signal that comprises a higher frequency resolution than a frequency resolution of the first modulated waveform signal;

wherein the delay in the rising edge of the first modulated waveform signal ‘td1[k]’ comprises a rising edge delay increment ‘dtL’, falling edge delay increment ‘dtH’ and a rising edge delay value calculated in the preceding waveform cycle ‘td1[k−1]’.

2. The semiconductor device of claim 1 wherein the delay logic is arranged to cause the first delay in the rising edge of the first modulated waveform and the second delay in the falling edge of the first modulated waveform signal, such that the second, refined modulated waveform signal further comprises a higher pulse width resolution than a pulse width resolution of the first modulated waveform signal generated by the timer logic.

3. The semiconductor device of claim 2 wherein the delay logic comprises a rising edge delay component arranged to cause the first delay in the rising edge of the first modulated waveform signal generated by the timer logic.

4. The semiconductor device of claim 2 wherein the delay logic comprises a falling edge delay component arranged to cause the second delay in the falling edge of the first modulated waveform signal generated by the timer logic.

5. The semiconductor device of claim 2 wherein the second delay in the falling edge of the first modulated waveform signal, ‘td 2 [k]’ comprises a falling edge delay increment ‘dt H ’, a falling edge delay increment ‘dt L ’, and a falling edge delay value calculated in the previous waveform cycle ‘td 2 [k−1]’.

6. The semiconductor device of claim 1 wherein the delay logic comprises a rising edge delay component arranged to cause the first delay in the rising edge of the first modulated waveform signal generated by the timer logic.

7. The semiconductor device of claim 6 wherein the second delay in the falling edge of the first modulated waveform signal, ‘td 2 [k]’ comprises a falling edge delay increment ‘dt H ’, a falling edge delay increment ‘dt L ’ and a falling edge delay value calculated in the previous waveform cycle ‘td 2 [k−1 ]’.

8. The semiconductor device of claim 1 wherein the delay logic comprises a falling edge delay component arranged to cause the second delay in the falling edge of the first modulated waveform signal generated by the timer logic.

9. The semiconductor device of claim 1 wherein the second delay in the falling edge of the first modulated waveform signal, ‘td 2 [k]’ comprises a falling edge delay increment ‘dt H ’, a falling edge delay increment ‘dt L ’ and a falling edge delay value calculated in the previous waveform cycle ‘td 2 [k−1]’.

10. The semiconductor device of claim 9 wherein if an edge delay ‘td 1(2) ’, is out of a delay module operational range <0,x*dt>, where dt =Period CLK /(x+1) and x ={1,2, . . . }, the delay comprises td,( 1(2) =n*Period CLK+ m*dt, where n=IntegerDivision(td 1(2) ,((x+1)*dt)) and m=ModuloDivision(td 1(2) ,((x+1)*dt)).

11. The semiconductor device of claim 10 wherein a high pulse width of the refined modulated waveform signal comprises ‘i* Period CLK +dt H ’ and a low pulse width of the refined modulated waveform signal comprises ‘j*Period CLK +dt I ’,

where: coefficients ‘i’ and ‘j’ are dependent upon a timer implementation and a duty cycle of the timer generated rough waveform signal, and

parameters ‘dt L ’ and ‘dt H ’ comprise rising and falling edge delay increments, respectively.

12. The semiconductor device of claim 11 wherein a period of the refined modulated waveform signal equals to ‘(i+j)*Period CLK +dt L +dt H ’.

13. The semiconductor device of claim 11 wherein the semiconductor device comprises a hardware adder module arranged to calculate refined edge delays for a modulated pulse, and to generate the timer hold clock pulse.

14. The semiconductor device of claim 1 wherein the delay logic comprises a timer hold clock line, operably coupled to the timer logic and arranged to enable the delay logic to cause the timer logic to suspend the first modulated waveform signal.

15. The semiconductor device of claim 14 wherein suspension of the first modulated waveform signal causes a re-synchronization of the first modulated waveform signal with the refined modulated waveform signal.

16. The semiconductor device of claim 1 wherein the delay logic comprises at least one adder module.

17. A method for generating a modulated waveform signal comprising:

receiving a first modulated waveform signal; and

generating a second, refined modulated waveform signal by causing a first delay in a rising edge of the first modulated waveform signal and causing a second delay in a falling edge of the first modulated waveform signal, such that the resulting second, refined modulated waveform signal comprises at least a higher frequency resolution than a frequency resolution of the first modulated waveform signal, wherein the delay in the rising edge of the first modulated waveform signal ‘td 1 [k]’ comprises a rising edge delay increment ‘dt L ’, falling edge delay increment ‘dt H ’ and a rising edge delay value calculated in the preceding waveform cycle ‘td 1 [k−1]’.

18. A computer-readable storage element having computer readable code stored thereon for programming a computer to perform a method for generating a modulated waveform signal, the code operable for:

receiving a first modulated waveform signal; and

generating a second, refined modulated waveform signal by causing a first delay in a rising edge of the first modulated waveform signal and causing a second delay in a falling edge of the first modulated waveform signal, such that the resulting second, refined modulated waveform signal comprises at least a higher frequency resolution than a frequency resolution of the first modulated waveform signal, wherein the delay in the rising edge of the first modulated waveform signal ‘td 1 [k]’ comprises a rising edge delay increment ‘td L ’, falling edge delay increment ‘td H ’ and a rising edge delay value calculated in the preceding waveform cycle ‘td 1 [k−1]’.

19. The computer-readable storage medium of claim 18 , wherein the computer readable storage medium comprises at least one of a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a ROM (Read Only Memory), a PROM (Programmable Read Only Memory), a EPROM (Erasable Programmable Read Only Memory), a EEPROM (Electrically Erasable Programmable Read Only Memory) and a Flash memory.

Assignments (31)