Method and apparatus for generating a clock signal
View Patent ↗An integrated circuit comprising oscillator circuitry is arranged to generate a clock signal for functional logic module of the integrated circuit. The oscillator circuitry comprises a plurality of propagation paths, and is arranged to apply a transition signal to inputs of the plurality of propagation paths, and to cause the output clock signal to transition based on a propagation of the transition signal through a determined set of the propagation paths.
1. An integrated circuit comprising:
oscillator circuitry arranged to generate a clock signal for a functional logic module of the integrated circuit, wherein
the clock signal comprises an output clock signal,
the oscillator circuitry comprises a plurality of propagation paths, OR logic, AND logic and multiplexer logic, wherein outputs of the plurality of propagation paths are operably coupled to both of inputs of the OR logic and inputs of the AND logic,
outputs of the OR logic and the AND logic are operably coupled to inputs of the multiplexer logic, and
an output of the multiplexer logic being arranged to provide the output clock signal, and
the oscillator circuitry is further configured to
apply a transition signal to inputs of the plurality of propagation paths, said multiplexer logic arranged to receive as a control signal, the transition signal, and
cause the output clock signal to transition based on a propagation of the transition signal through a determined set of the propagation paths.
2. The integrated circuit of claim 1 , wherein the oscillator circuitry comprises:
transition logic comprises the OR logic, the AND logic, and the multiplexer logic, operably coupled to the outputs of the plurality of propagation paths, wherein
the transition logic is arranged to cause the output clock signal to transition upon the propagation of the transition signal through the determined set of propagation paths fulfilling a propagation criteria.
3. The integrated circuit of claim 2 , wherein the transition logic is further arranged to cause the output clock signal to transition from a logic “0” value to a logic “1” value based on a worst case propagation of the transition signal through the determined set of propagation paths and to transition from the logic “1” value to the logic “0” value based on the worst case propagation of the transition signal through the determined set of propagation paths.
4. The integrated circuit of claim 2 , further comprising:
one or more switching elements, wherein
the output of one or more of the propagation paths is operably coupled to the transition logic via the one or more switching elements, and
each switching element is arranged to selectively mask its respective propagation path.
5. The integrated circuit of claim 2 , wherein the multiplexer logic is arranged, in response to the transition signal comprising a transition from a “0” value to a “1” value, to output a signal from either the AND logic or the OR logic.
6. The integrated circuit of claim 1 , wherein the oscillator circuitry and the functional logic module are operably coupled to a common supply voltage.
7. The integrated circuit of claim 1 , wherein the functional logic module comprises the oscillator circuitry, an internal supply voltage, and functional logic, a common supply voltage comprises the internal supply voltage, the output clock signal is operably coupled to the functional logic, and the oscillator circuitry is operably coupled to the internal supply voltage of the functional logic module.
8. The integrated circuit of claim 1 , wherein the multiplexer logic is arranged, in response to the transition signal comprising a transition from a “0” value to a “1” value, to output a signal from either the AND logic or the OR logic.
9. The integrated circuit of claim 1 , wherein the oscillator circuitry is arranged to apply the transition signal comprising an inverse of the output clock signal to the inputs of the plurality of propagation paths.
10. The integrated circuit of claim 9 , wherein the oscillator circuitry further comprises a second AND logic arranged to receive as an input the inverse of the output clock signal, and to output the transition signal.
11. The integrated circuit of claim 10 , wherein the second AND logic is further arranged to receive as an input an oscillator circuitry enable signal.
12. The integrated circuit of claim 1 , wherein at least one of the propagation paths comprises at least one from a group of:
a replica of a critical path within the functional logic module;
a statistical-based cell group for a critical path within the functional logic module;
a defined cell type path; and
a defined cell size path.
13. A method for generating a clock signal for a functional logic module within an integrated circuit comprising oscillator circuitry, the method comprising:
generating the clock signal by the oscillator circuitry including a plurality of propagation paths, and a multiplexer logic, wherein
the clock signal comprises an output clock signal, and
an output of the multiplexer logic being arranged to provide the output clock signal; and
applying a transition signal to inputs of the plurality of propagation paths, wherein the multiplexer logic is arranged to receive as a control signal, the transition signal;
performing an AND operation and an OR operation on outputs of the plurality of propagation paths, in response to the transition signal;
multiplexing the results of said performing the AND operation and the OR operation to generate the output clock signal, in response to the transition signal; and
causing the output clock signal of the oscillator circuitry to transition based on a propagation of the transition signal through at least one of the propagation paths.
14. The method of claim 13 , further comprising: causing the output clock signal to transition upon propagation of the transition signal through the at least one of the propagation paths, wherein the transition fulfills a propagation criteria.
15. The method of claim 14 , further comprising:
causing the output clock signal to transition based on a worst case propagation of the transition signal through the at least one of the propagation paths.
16. The method of claim 13 , wherein said performing the AND operation and the OR operation further comprises:
performing the AND operation in response to the transition signal comprising a value; and
performing the OR operation in response to the transition signal comprising a value, wherein
the transition signal comprises an inverse of the output clock signal.
17. An integrated circuit comprising:
oscillator circuitry arranged to generate a clock signal for a functional logic module of the integrated circuit, wherein
the clock signal comprises an output clock signal,
the oscillator circuitry comprises a plurality of propagation paths and a multiplexer logic, wherein
an output of the multiplexer logic being arranged to provide the output clock signal, and
the oscillator circuitry is further configured to
apply a transition signal to inputs of the plurality of propagation paths, said multiplexer logic arranged to receive as a control signal, the transition signal,
wherein the transition signal comprising an inverse of the output clock signal, and
cause the output clock signal to transition based on a propagation of the transition signal through a determined set of the propagation paths.
18. The integrated circuit of claim 17 , wherein the oscillator circuitry comprises:
transition logic operably coupled to outputs of the plurality of propagation paths, wherein the transition logic is arranged to cause the output clock signal to transition upon the propagation of the transition signal through the determined set of propagation paths fulfilling a propagation criteria.
19. The integrated circuit of claim 17 ,
wherein at least one of the propagation paths comprises at least one from a group of:
a replica of a critical path within the functional logic module;
a statistical-based cell group for a critical path within the functional logic module; a defined cell type path; and a defined cell size path.
20. A method for generating a clock signal for a functional logic module within an integrated circuit comprising oscillator circuitry, the method comprising:
generating a clock signal by the oscillator circuitry including a plurality of propagation paths, and a multiplexer logic, wherein
the clock signal comprises an output clock signal, and
an output of the multiplexer logic being arranged to provide the output clock signal;
applying a transition signal to inputs of the plurality of propagation paths, wherein
the multiplexer logic is arranged to receive as a control signal, the transition signal, wherein
the transition signal comprising an inverse of the output clock signal; and
causing the output clock signal of the oscillator circuitry to transition based on a propagation of the transition signal through at least one of the propagation paths.